cisc-0.2, branch new-instruction-handlerAn emulator for the Sux instruction set.https://git.b0nk.xyz/cisc-0.2.git/atom?h=new-instruction-handler2022-02-18T14:05:01Zigen: Fixed a typo in `lex_comp_stmt()`.2022-02-18T14:05:01Zmrb0nk500b0nk@b0nk.xyz2022-02-18T14:01:49Zurn:sha1:f00dcc0b9d2588936d8a64dcfa64620a07a05c6digen: Add Makefile.2022-02-18T14:05:01Zmrb0nk500b0nk@b0nk.xyz2022-02-18T01:16:58Zurn:sha1:bb88d7c8640a89ed943773ff5b7c34a67377fc9digen: Fixed some compilation errors, and warnings.2022-02-18T14:05:01Zmrb0nk500b0nk@b0nk.xyz2022-02-18T01:15:59Zurn:sha1:ab0517cc4a6077c756d03c7c19311f5bd841d856igen: Did some more work on it.2022-02-18T14:05:01Zmrb0nk500b0nk@b0nk.xyz2022-02-17T20:42:31Zurn:sha1:524cfc23b15e1067076e45b056cb1d84e87e66cbigen: Start work on writing a preprocessor.2022-02-18T14:05:01Zmrb0nk500b0nk@b0nk.xyz2022-02-16T21:05:00Zurn:sha1:5f753ddee7d935e0ba4750a6a8c26fe056c77612igen: Start work on a better lexer.2022-02-18T14:05:01Zmrb0nk500b0nk@b0nk.xyz2022-02-15T22:49:29Zurn:sha1:722c7f08e409d1f6f3a26bda666c15d7082f52e3
The other one I was about to do would've been harder
to read, and understand.
So, I've decided to write a more readable version.
igen: Start work on writing an instruction handler2022-02-14T00:20:59Zmrb0nk500b0nk@b0nk.xyz2022-02-14T00:20:59Zurn:sha1:f478e6c1223cc8370fa51d44b9244ec25be99788
generator.
This will make it easier in the long run to modify
instructions, add new instructions, and move the opcode
tables around.
sux.h: Add bitmask for b register addressing mode.2022-02-14T00:16:43Zmrb0nk500b0nk@b0nk.xyz2022-02-14T00:16:43Zurn:sha1:6833f6bc2a5730169084c74d8e8fc0b76666b2a0sux.{c,h}, opcode.h, disasm.c: Add code to use the new2022-02-09T17:45:26Zmrb0nk500b0nk@b0nk.xyz2022-02-09T17:45:26Zurn:sha1:8d9190cb14f287193196f422d49dbca0809980c7
instruction handler for reading the interrupt vectors.
sux.h: Fix some bugs in the interrupt bitmasks.2022-02-09T17:42:58Zmrb0nk500b0nk@b0nk.xyz2022-02-09T17:41:21Zurn:sha1:b9fdf56717af2a9e7c9224610082bb026c86a87e