cisc-0.2, branch rev1An emulator for the Sux instruction set.https://git.b0nk.xyz/cisc-0.2.git/atom?h=rev12019-11-26T19:22:17Zrev1 of Sux has been completed!2019-11-26T19:22:17Zmrb0nk500b0nk@b0nk.xyz2019-11-26T19:22:17Zurn:sha1:10ec62e8025eb43d1a096fb0962049670c3c148c
I have now implemented BRK, and RTI.
Also, BieHDC, and I will both be working on rev2.
Revamped the entire emulator.2019-11-26T05:33:20Zmrb0nk500b0nk@b0nk.xyz2019-11-26T05:33:20Zurn:sha1:c1e735ec8b0481c1ebc631cd495a10f72e47ba32
I finally implemented the other addressing modes, and
added a Makefile.
Not sure when I will start work on rev2 of Sux, but it
will be sometime soon.
Fixed some bugs in some instructions.2019-11-20T22:35:38Zmrb0nk500b0nk@b0nk.xyz2019-11-20T22:35:38Zurn:sha1:988c81ae76ab0da47db8938c14865d6e5b3a8024
Fixed stack based instructions.
Fixed the rotate instructions.
Added carry to the shift instructions.
The emulator is working!!!2019-11-18T04:04:31Zmrb0nk500b0nk@b0nk.xyz2019-11-18T04:04:31Zurn:sha1:c42888e7e09b0a45c6b02534829eac06506834a6Implemented memory based instructions, and removed2019-11-16T18:16:38Zmrb0nk500b0nk@b0nk.xyz2019-11-16T18:16:38Zurn:sha1:f070b984f4d1af513d215bd24e6b1951e3ee86cb
some unneeded instructions.
Actually set the Processor Status flags correctly, and2019-11-13T17:06:03Zmrb0nk500b0nk@b0nk.xyz2019-11-13T17:06:03Zurn:sha1:d3879906fb63fdeab9d28f651d2242eade251402
revamp some other stuff.
Started work on simultanious multithreading, and branching.2019-11-12T01:43:05Zmrb0nk500b0nk@b0nk.xyz2019-11-12T01:43:05Zurn:sha1:a5c33b00e110928e86fa08f91f8ccab86b9a9eb1Added more instructions to the ALU.2019-11-11T20:07:42Zmrb0nk500b0nk@b0nk.xyz2019-11-11T20:07:42Zurn:sha1:e3fc06b083598f244b3949e06d4ffbd3d2b235ccAdded comments in opcode.h, and started work on the2019-11-11T18:27:17Zmrb0nk500b0nk@b0nk.xyz2019-11-11T18:27:17Zurn:sha1:03cf68ff44084f76de7eae2fe93731312f493eb7
Sux emulator.
Initial commit.2019-11-10T18:55:44Zmrb0nk500b0nk@b0nk.xyz2019-11-10T18:55:44Zurn:sha1:1a8c15676cc6aea4a5527d729489e523816cae04