diff options
Diffstat (limited to 'sux.c')
| -rw-r--r-- | sux.c | 221 |
1 files changed, 97 insertions, 124 deletions
@@ -146,6 +146,14 @@ void *run(void *args) { if (optype[opcode] != IMPL) { address.u64 = get_addr(cpu, &tmpaddr, opcode, prefix, thread); setreg_sw(value.u8, 0, addr, address.u64, prefix, 0, RS); + if (optype[opcode] == REL) { + switch ((prefix >> 4) & 3) { + default: address.u64 = cpu->pc + (int8_t )value.u8[0] ; break; + case 1 : address.u64 = cpu->pc + (int16_t)value.u16[0]; break; + case 2 : address.u64 = cpu->pc + (int32_t)value.u32[0]; break; + case 3 : address.u64 = cpu->pc + (int64_t)value.u64 ; break; + } + } #if getclk ++iclk; #endif @@ -165,123 +173,105 @@ void *run(void *args) { #endif #endif switch(opcode) { - case CPS: /* Clear Processor Status. */ + case CPS_IMP: /* Clear Processor Status. */ cpu->ps.u64 = 0; break; - case AAB: /* Add Accumulator with carry by B register. */ + case AAB_IMP: /* Add Accumulator with carry by B register. */ value.u64 = cpu->b; /* Falls Through. */ - case ADC: /* ADC Immediate. */ + case ADC_IMM: /* ADC Immediate. */ case ADC_AB: /* ADC Absolute. */ case ADC_Z: /* ADC Zero Matrix. */ adc(cpu, value.u64, thread); break; - case PHP: push(cpu, value.u64, cpu->ps.u64, thread); break; /* PusH Processor status to stack. */ - case PHA: push(cpu, value.u64, cpu->a , thread); break; /* PusH Accumulator to stack. */ - case PHB: push(cpu, value.u64, cpu->b , thread); break; /* PusH B register to stack. */ - case PHY: push(cpu, value.u64, cpu->y , thread); break; /* PusH Y register to stack. */ - case PHX: push(cpu, value.u64, cpu->x , thread); break; /* PusH X register to stack. */ - case TAY: /* Transfer Accumulator to Y. */ - case TAX: /* Transfer Accumulator to Y. */ - case TYX: /* Transfer Y to X. */ - case TYA: /* Transfer Y to Accumulator. */ - case TXA: /* Transfer X to Accumulator. */ - case TXY: /* Transfer X to Y. */ - case TAB: /* Transfer Accumulator to B. */ - case TSX: /* Transfer Stack pointer to X. */ - case TBA: /* Transfer B to Accumulator. */ - case TXS: /* Transfer X to Stack pointer. */ + case PHP_IMP: push(cpu, cpu->ps.u64, 0, thread); break; /* PusH Processor status to stack. */ + case PHA_IMP: push(cpu, cpu->a , prefix, thread); break; /* PusH Accumulator to stack. */ + case PHB_IMP: push(cpu, cpu->b , prefix, thread); break; /* PusH B register to stack. */ + case PHY_IMP: push(cpu, cpu->y , prefix, thread); break; /* PusH Y register to stack. */ + case PHX_IMP: push(cpu, cpu->x , prefix, thread); break; /* PusH X register to stack. */ + case TAY_IMP: /* Transfer Accumulator to Y. */ + case TAX_IMP: /* Transfer Accumulator to Y. */ + case TYX_IMP: /* Transfer Y to X. */ + case TYA_IMP: /* Transfer Y to Accumulator. */ + case TXA_IMP: /* Transfer X to Accumulator. */ + case TXY_IMP: /* Transfer X to Y. */ + case TAB_IMP: /* Transfer Accumulator to B. */ + case TSX_IMP: /* Transfer Stack pointer to X. */ + case TBA_IMP: /* Transfer B to Accumulator. */ + case TXS_IMM: /* Transfer X to Stack pointer. */ transfer(cpu, value.u64, opcode, prefix, thread); break; - case JMP: /* JMP Absolute. */ + case BRA_REL: /* BRA Relative. */ + case JMP_AB: /* JMP Absolute. */ case JMP_Z: /* JMP Zero Matrix. */ case JMP_IN: /* JMP Indirect. */ cpu->pc = address.u64; break; - case SAB: /* Subtract Accumulator with carry by B register. */ + case SAB_IMP: /* Subtract Accumulator with carry by B register. */ value.u64 = cpu->b; /* Falls Through. */ - case SBC: /* SBC Immediate. */ + case SBC_IMM: /* SBC Immediate. */ case SBC_AB: /* SBC Absolute. */ case SBC_Z: /* SBC Zero Matrix. */ sbc(cpu, value.u64, thread); break; - case PLP: cpu->ps.u64 = pull(cpu, value.u64, thread); break; /* PuLl Processor status from stack. */ - case PLA: cpu->a = pull(cpu, value.u64, thread); break; /* PuLl Accumulator from stack. */ - case PLB: cpu->b = pull(cpu, value.u64, thread); break; /* PuLl B register from stack. */ - case PLY: cpu->y = pull(cpu, value.u64, thread); break; /* PuLl Y register from stack. */ - case PLX: cpu->x = pull(cpu, value.u64, thread); break; /* PuLl X register from stack. */ + case PLP_IMP: cpu->ps.u64 = pull(cpu, 0, thread); break; /* PuLl Processor status from stack. */ + case PLA_IMP: cpu->a = pull(cpu, prefix, thread); break; /* PuLl Accumulator from stack. */ + case PLB_IMP: cpu->b = pull(cpu, prefix, thread); break; /* PuLl B register from stack. */ + case PLY_IMP: cpu->y = pull(cpu, prefix, thread); break; /* PuLl Y register from stack. */ + case PLX_IMP: cpu->x = pull(cpu, prefix, thread); break; /* PuLl X register from stack. */ break; - case ABA: /* bitwise And with Accumulator, and B register. */ + case ABA_IMP: /* bitwise And with Accumulator, and B register. */ value.u64 = cpu->b; /* Falls Through. */ - case AND: /* AND Immediate. */ + case AND_IMM: /* AND Immediate. */ case AND_AB: /* AND Absolute. */ case AND_Z: /* AND Zero Matrix. */ and(cpu, value.u64, thread); break; - case STT: /* STart Thread. */ - /*cpu->crt |= value; - for (uint8_t i = 0; i < 7; i++) { - if ((value >> i) & 1) { - address = (uint64_t)addr[tv+(i<<3)] - | (uint64_t)addr[tv+1+(i<<3)] << 8 - | (uint64_t)addr[tv+2+(i<<3)] << 16 - | (uint64_t)addr[tv+3+(i<<3)] << 24 - | (uint64_t)addr[tv+4+(i<<3)] << 32 - | (uint64_t)addr[tv+5+(i<<3)] << 40 - | (uint64_t)addr[tv+6+(i<<3)] << 48 - | (uint64_t)addr[tv+7+(i<<3)] << 56; - cpu->pc[i+1] = address; - } - }*/ - break; - case BPO: /* BPO Absolute. */ - case BPO_Z: /* BPO Zero Matrix. */ + case BPO_REL: /* BPO Relative. */ if (!getflag(N)) { cpu->pc = address.u64; } break; - case OAB: /* bitwise Or with Accumulator, and B register. */ + case OAB_IMP: /* bitwise Or with Accumulator, and B register. */ value.u64 = cpu->b; /* Falls Through. */ - case ORA: /* ORA Immediate. */ + case ORA_IMM: /* ORA Immediate. */ case ORA_AB: /* ORA Absolute. */ case ORA_Z: /* ORA Zero Matrix. */ or(cpu, value.u64, thread); break; - case SEI: /* SEt Interrupt. */ + case SEI_IMP: /* SEt Interrupt. */ setflag(1, I); break; - case BNG: /* BNG Absolute. */ - case BNG_Z: /* BNG Zero Matrix. */ + case BNG_REL: /* BNG Relative. */ if (getflag(N)) { cpu->pc = address.u64; } break; - case XAB: /* bitwise Xor with Accumulator, and B register. */ + case XAB_IMP: /* bitwise Xor with Accumulator, and B register. */ value.u64 = cpu->b; /* Falls Through. */ - case XOR: /* XOR Immediate. */ + case XOR_IMM: /* XOR Immediate. */ case XOR_AB: /* XOR Absolute. */ case XOR_Z: /* XOR Zero Matrix. */ xor(cpu, value.u64, thread); break; - case CLI: /* CLear Interrupt. */ + case CLI_IMP: /* CLear Interrupt. */ setflag(0, I); break; - case BCS: /* BCS Absolute. */ - case BCS_Z: /* BCS Zero Matrix. */ + case BCS_REL: /* BCS Relative. */ if (getflag(C)) { cpu->pc = address.u64; } break; - case LLB: /* Logical shift Left accumulator by B. */ + case LLB_IMP: /* Logical shift Left accumulator by B. */ value.u64 = cpu->b; /* Falls Through. */ - case LSL: /* LSL Immediate. */ + case LSL_IMM: /* LSL Immediate. */ case LSL_AB: /* LSL Absolute. */ case LSL_Z: /* LSL Zero Matrix. */ lsl(cpu, value.u64, thread); break; - case SEC: /* SEt Carry flag.*/ + case SEC_IMP: /* SEt Carry flag.*/ setflag(1, C); break; - case STA: /* STA Absolute. */ + case STA_AB: /* STA Absolute. */ case STA_Z: /* STA Zero Matrix. */ case STA_ZX: /* STA Zero Matrix, Indexed with X. */ case STA_ZY: /* STA Zero Matrix, Indexed with Y. */ @@ -290,19 +280,17 @@ void *run(void *args) { case STA_IY: /* STA Indirect Indexed. */ store(cpu, address.u64, cpu->a, prefix, thread); break; - case STY: /* STY Absolute. */ + case STY_AB: /* STY Absolute. */ case STY_Z: /* STY Zero Matrix. */ - case STY_ZX: /* STY Zero Matrix, Indexed with X. */ case STY_IN: /* STY Indirect. */ store(cpu, address.u64, cpu->y, prefix, thread); break; - case STX: /* STX Absolute. */ + case STX_AB: /* STX Absolute. */ case STX_Z: /* STX Zero Matrix. */ - case STX_ZY: /* STX Zero Matrix, Indexed with Y. */ case STX_IN: /* STX Indirect. */ store(cpu, address.u64, cpu->x, prefix, thread); break; - case STB: /* STB Absolute. */ + case STB_AB: /* STB Absolute. */ case STB_Z: /* STB Zero Matrix. */ case STB_ZX: /* STB Zero Matrix, Indexed with X. */ case STB_ZY: /* STB Zero Matrix, Indexed with Y. */ @@ -311,30 +299,29 @@ void *run(void *args) { case STB_IY: /* STB Indirect Indexed. */ store(cpu, address.u64, cpu->b, prefix, thread); break; - case BCC: /* BCC Absolute. */ - case BCC_Z: /* BCC Zero Matrix. */ + case BCC_REL: /* BCC Relative. */ if (!getflag(C)) { cpu->pc = address.u64; } break; - case LRB: /* Logical shift Right accumulator by B. */ + case LRB_IMP: /* Logical shift Right accumulator by B. */ value.u64 = cpu->b; /* Falls Through. */ - case LSR: /* LSR Immediate. */ + case LSR_IMM: /* LSR Immediate. */ case LSR_AB: /* LSR Absolute. */ case LSR_Z: /* LSR Zero Matrix. */ lsr(cpu, value.u64, thread); break; - case ARB: /* Arithmetic shift Right accumulator by B. */ + case ARB_IMP: /* Arithmetic shift Right accumulator by B. */ value.u64 = cpu->b; /* Falls Through. */ - case ASR: /* ASR Immediate. */ + case ASR_IMM: /* ASR Immediate. */ case ASR_AB: /* ASR Absolute. */ case ASR_Z: /* ASR Zero Matrix. */ asr(cpu, value.u64, thread); break; - case CLC: /* CLear Carry flag. */ + case CLC_IMP: /* CLear Carry flag. */ setflag(0, C); break; - case LDB: /* LDB Immediate. */ + case LDB_IMM: /* LDB Immediate. */ case LDB_AB: /* LDB Absolute. */ case LDB_Z: /* LDB Zero Matrix. */ case LDB_ZX: /* LDB Zero Matrix, Indexed with X. */ @@ -344,7 +331,7 @@ void *run(void *args) { case LDB_IY: /* LDB Indirect Indexed. */ cpu->b = load(cpu, address.u64, cpu->b, prefix, thread); break; - case LDA: /* LDA Immediate. */ + case LDA_IMM: /* LDA Immediate. */ case LDA_AB: /* LDA Absolute. */ case LDA_Z: /* LDA Zero Matrix. */ case LDA_ZX: /* LDA Zero Matrix, Indexed with X. */ @@ -354,75 +341,69 @@ void *run(void *args) { case LDA_IY: /* LDA Indirect Indexed. */ cpu->a = load(cpu, address.u64, cpu->a, prefix, thread); break; - case LDY: /* LDY Immediate. */ + case LDY_IMM: /* LDY Immediate. */ case LDY_AB: /* LDY Absolute. */ case LDY_Z: /* LDY Zero Matrix. */ - case LDY_ZX: /* LDY Zero Matrix, Indexed with X. */ case LDY_IN: /* LDY Indirect. */ cpu->y = load(cpu, address.u64, cpu->y, prefix, thread); break; - case LDX: /* LDX Immediate. */ + case LDX_IMM: /* LDX Immediate. */ case LDX_AB: /* LDX Absolute. */ case LDX_Z: /* LDX Zero Matrix. */ - case LDX_ZY: /* LDX Zero Matrix, Indexed with Y. */ case LDX_IN: /* LDX Indirect. */ cpu->x = load(cpu, address.u64, cpu->x, prefix, thread); break; - case BEQ: /* BEQ Absolute. */ - case BEQ_Z: /* BEQ Zero Matrix. */ + case BEQ_REL: /* BEQ Relative. */ if (getflag(Z)) { cpu->pc = address.u64; } break; - case RLB: /* Rotate Left accumulator by B. */ + case RLB_IMP: /* Rotate Left accumulator by B. */ value.u64 = cpu->b; /* Falls Through. */ - case ROL: /* ROL Immediate. */ + case ROL_IMM: /* ROL Immediate. */ case ROL_AB: /* ROL Absolute. */ case ROL_Z: /* ROL Zero Matrix. */ rol(cpu, value.u64, thread); break; - case BNE: /* BNE Absolute. */ - case BNE_Z: /* BNE Zero Matrix. */ + case BNE_REL: /* BNE Relative. */ if (!getflag(Z)) { cpu->pc = address.u64; } break; - case RRB: /* Rotate Right accumulator by B. */ + case RRB_IMP: /* Rotate Right accumulator by B. */ value.u64 = cpu->b; /* Falls Through. */ - case ROR: /* ROR Immediate. */ + case ROR_IMM: /* ROR Immediate. */ case ROR_AB: /* ROR Absolute. */ case ROR_Z: /* ROR Zero Matrix. */ ror(cpu, value.u64, thread); break; - case BVS: /* BVS Absolute. */ - case BVS_Z: /* BVS Zero Matrix. */ + case BVS_REL: /* BVS Relative. */ if (getflag(V)) { cpu->pc = address.u64; } break; - case MAB: /* Multiply Accumulator by B. */ + case MAB_IMP: /* Multiply Accumulator by B. */ value.u64 = cpu->b; /* Falls Through. */ - case MUL: /* MUL Immediate. */ + case MUL_IMM: /* MUL Immediate. */ case MUL_AB: /* MUL Absolute. */ case MUL_Z: /* MUL Zero Matrix. */ mul(cpu, value.u64, thread); break; - case BVC: /* BVC Absolute. */ - case BVC_Z: /* BVC Zero Matrix. */ + case BVC_REL: /* BVC Relative. */ if (!getflag(V)) { cpu->pc = address.u64; } break; - case DIV: /* DIV Immediate. */ - case DAB: /* Divide Accumulator by B. */ + case DIV_IMM: /* DIV Immediate. */ + case DAB_IMP: /* Divide Accumulator by B. */ case DIV_AB: /* DIV Absolute. */ case DIV_Z: /* DIV Zero Matrix. */ divd(cpu, value.u64, opcode, thread); break; - case CLV: /* CLear oVerflow flag. */ + case CLV_IMP: /* CLear oVerflow flag. */ setflag(0, V); break; - case CPB: /* CPB Immediate. */ + case CPB_IMM: /* CPB Immediate. */ case CPB_AB: /* CPB Absolute. */ case CPB_Z: /* CPB Zero Matrix. */ case CPB_IN: /* CPB Indirect. */ @@ -430,9 +411,9 @@ void *run(void *args) { case CPB_IY: /* CPB Indirect Indexed. */ cmp(cpu, value.u64, cpu->b, thread); break; - case CAB: /* Compare Accumulator, and B. */ + case CAB_IMP: /* Compare Accumulator, and B. */ value.u64 = cpu->b; /* Falls Through. */ - case CMP: /* CMP Immediate. */ + case CMP_IMM: /* CMP Immediate. */ case CMP_AB: /* CMP Absolute. */ case CMP_Z: /* CMP Zero Matrix. */ case CMP_IN: /* CMP Indirect. */ @@ -440,34 +421,26 @@ void *run(void *args) { case CMP_IY: /* CMP Indirect Indexed. */ cmp(cpu, value.u64, cpu->a, thread); break; - case CPY: /* CPY Immediate. */ + case CPY_IMM: /* CPY Immediate. */ case CPY_AB: /* CPY Absolute. */ case CPY_Z: /* CPY Zero Matrix. */ - case CPY_IN: /* CPY Indirect. */ cmp(cpu, value.u64, cpu->y, thread); break; - case CPX: /* CPX Immediate. */ + case CPX_IMM: /* CPX Immediate. */ case CPX_AB: /* CPX Absolute. */ case CPX_Z: /* CPX Zero Matrix. */ - case CPX_IN: /* CPX Indirect. */ cmp(cpu, value.u64, cpu->x, thread); break; - case ENT: /* ENd Thread. */ - /* cpu->crt &= ~value; - for (uint8_t i = 0; i < 7; i++) - if ((value >> i) & 1) - cpu->pc[i+1] = cpu->pc[0]+(i+1);*/ - break; - case INC: cpu->a = idr(cpu, cpu->a, 1, thread); break; - case INB: cpu->b = idr(cpu, cpu->b, 1, thread); break; - case INY: cpu->y = idr(cpu, cpu->y, 1, thread); break; - case INX: cpu->x = idr(cpu, cpu->x, 1, thread); break; - case DEC: cpu->a = idr(cpu, cpu->a, 0, thread); break; - case DEB: cpu->b = idr(cpu, cpu->b, 0, thread); break; - case DEY: cpu->y = idr(cpu, cpu->y, 0, thread); break; - case DEX: cpu->x = idr(cpu, cpu->x, 0, thread); break; + case INC_IMP: cpu->a = idr(cpu, cpu->a, 1, thread); break; + case INB_IMP: cpu->b = idr(cpu, cpu->b, 1, thread); break; + case INY_IMP: cpu->y = idr(cpu, cpu->y, 1, thread); break; + case INX_IMP: cpu->x = idr(cpu, cpu->x, 1, thread); break; + case DEC_IMP: cpu->a = idr(cpu, cpu->a, 0, thread); break; + case DEB_IMP: cpu->b = idr(cpu, cpu->b, 0, thread); break; + case DEY_IMP: cpu->y = idr(cpu, cpu->y, 0, thread); break; + case DEX_IMP: cpu->x = idr(cpu, cpu->x, 0, thread); break; case JSR_IN: /* JSR Indirect. */ - case JSR: /* Jump to SubRoutine. */ + case JSR_AB: /* Jump to SubRoutine. */ case JSR_Z: /* JSR Zero Matrix. */ value.u64 = cpu->pc; setreg(addr, -, (cpu->stk_st << 16)+cpu->sp, value.u8, +, 0, 7); @@ -478,12 +451,12 @@ void *run(void *args) { case INC_Z: /* INC Zero Matrix. */ idm(cpu, address.u64, prefix, 1, thread); break; - case NOP: /* No OPeration. */ + case NOP_IMP: /* No OPeration. */ break; - case RTI: /* ReTurn from Interrupt routine. */ + case RTI_IMP: /* ReTurn from Interrupt routine. */ cpu->sp += 1; cpu->ps.u8[thread] = addr[(cpu->stk_st << 16)+(cpu->sp)]; /* Falls through. */ - case RTS: /* ReTurn from Subroutine. */ + case RTS_IMP: /* ReTurn from Subroutine. */ cpu->sp += 8; setreg(value.u8, +, 0, addr, -, (cpu->stk_st << 16)+cpu->sp, 7); cpu->pc = value.u64; @@ -492,9 +465,9 @@ void *run(void *args) { case DEC_Z: /* DEC Zero Matrix. */ idm(cpu, address.u64, prefix, 0, thread); break; - case BRK: /* BReaK. */ - case WAI: /* WAit for Interrupt. */ - if (opcode == WAI) { + case BRK_IMP: /* BReaK. */ + case WAI_IMP: /* WAit for Interrupt. */ + if (opcode == WAI_IMP) { pthread_mutex_lock(&main_mutex); pthread_cond_signal(&main_cond); pthread_mutex_unlock(&main_mutex); @@ -508,7 +481,7 @@ void *run(void *args) { cpu->sp -= 9; setflag(1, I); setreg(value.u8, +, 0, addr, +, (opcode == BRK) ? 0xFFE0 : 0xFFA0, 7); - if (opcode == WAI) { + if (opcode == WAI_IMP) { kbd_rdy &= (uint8_t)~(1 << thread); } cpu->pc = value.u64; |