summaryrefslogtreecommitdiff
path: root/sux.h
diff options
context:
space:
mode:
Diffstat (limited to 'sux.h')
-rw-r--r--sux.h436
1 files changed, 403 insertions, 33 deletions
diff --git a/sux.h b/sux.h
index 5d8ded7..6b8a7f6 100644
--- a/sux.h
+++ b/sux.h
@@ -37,6 +37,15 @@ extern uint8_t end;
#define setflag(flag, bit) ((flag)) ? (cpu->ps.u8[thread] |= bit) : (cpu->ps.u8[thread] &= ~bit)
#define getflag(bit) (cpu->ps.u8[thread] & bit)
+#define ORTHO_1CC(mne, cc) \
+ mne##_R##cc: case mne##_M##cc
+
+#define ORTHO_1OP(mne) \
+ mne##_R: case mne##_M
+
+#define ORTHO_2OP(mne) \
+ mne##_RR: case mne##_RM: case mne##_MR: case mne##_MM
+
extern pthread_mutex_t mutex;
extern pthread_mutex_t main_mutex;
extern pthread_cond_t cond;
@@ -44,7 +53,7 @@ extern pthread_cond_t main_cond;
#if debug
extern void print_regs(struct sux *cpu, uint8_t lines, uint8_t thread);
-extern void disasm(struct sux *cpu, uint8_t lines, uint8_t opcode, uint8_t prefix, uint8_t ext_prefix, uint8_t prefix2, uint8_t thread);
+extern void disasm(struct sux *cpu, uint8_t lines, uint8_t opcode, uint8_t prefix, uint8_t ext_prefix, uint8_t prefix2, uint8_t *op_type, uint8_t *op_id, uint8_t thread);
#endif
/*#define KEYBUF_SIZE 0x40
@@ -88,6 +97,23 @@ static /*inline*/ uint8_t get_addrsize(uint8_t prefix, uint8_t addrmode) {
return 0xFF;
}
+static /*inline*/ uint8_t get_ortho_addrsize(uint8_t prefix, uint8_t addrmode) {
+ uint8_t type = IMM;
+ switch (addrmode) {
+ case MEM_ABS :
+ case MEM_ABSR :
+ case MEM_AIND :
+ case MEM_AINDR:
+ case MEM_ARIND: type = ABS; break;
+ case MEM_ZM :
+ case MEM_ZMR :
+ case MEM_IND :
+ case MEM_ZINDR:
+ case MEM_ZRIND: type = ZM; break;
+ }
+ return get_addrsize(prefix, type);
+}
+
static /*inline*/ uint8_t isrw(uint8_t opcode, uint8_t ext_prefix) {
if ((ext_prefix & 0xD) == 0xD) {
switch (ext_prefix >> 4) {
@@ -480,12 +506,84 @@ static /*inline*/ uint64_t get_addr(struct sux *cpu, uint8_t opcode, uint8_t pre
return address;
}
+static /*inline*/ uint64_t get_ortho_addr(struct sux *cpu, uint8_t prefix, uint64_t address, operand *op, uint64_t *value, uint8_t *op_type, uint8_t *op_id, uint8_t inc_pc, uint8_t inc_clk, uint8_t thread) {
+ for (int i = 0; i < 2; i++) {
+ union reg tmp;
+ tmp.u64 = 0;
+ op[i].type = op_type[i];
+ op[i].id = op_id[i];
+ op[i].value = 0;
+ op[i].rind[0] = 0xFF;
+ op[i].rind[1] = 0xFF;
+ if (op[i].type) {
+ int inst_size = 0;
+ int addr_size = get_ortho_addrsize(prefix, op[i].id);
+ int rs = (1 << (prefix >> 4));
+ int is_rind = (op[i].id != MEM_ABS && op[i].id != MEM_ZM && op[i].id != MEM_AIND && op[i].id != MEM_IND && op[i].id != MEM_IMM);
+ if (is_rind) {
+ inst_size = (op[i].id == MEM_SIB)+1;
+ tmp.u64 = read_value(cpu, 0, address, inst_size-1, 0, 0);
+ if (inc_pc) {
+ address += inst_size;
+ }
+ op[i].rind[0] = (tmp.u8[inst_size-1] & 0x0F);
+ op[i].rind[1] = (tmp.u8[inst_size-1] >> 4);
+ if (op[i].rind[1] == op[i].rind[0]) {
+ op[i].rind[1] = 0xFF;
+ }
+ op[i].scale = (inst_size == 2) ? tmp.u8[0] : 0;
+ }
+ if (addr_size != 0xFF || (rs && op[i].id == MEM_IMM)) {
+ inst_size = (addr_size != 0xFF) ? addr_size+1 : rs;
+ op[i].value = read_value(cpu, 0, address, inst_size-1, inc_clk, 0);
+ value[i] = op[i].value;
+ if (inc_pc) {
+ address += inst_size;
+ }
+ }
+ if (is_rind) {
+ for (int j = 0; j < 2 && op[i].rind[j] != 0xFF; j++) {
+ uint64_t reg;
+ switch (op[i].rind[j]) {
+ case REG_A : reg = cpu->a; break;
+ case REG_B : reg = cpu->b; break;
+ case REG_X : reg = cpu->x; break;
+ case REG_Y : reg = cpu->y; break;
+ case REG_E : reg = cpu->e; break;
+ case REG_C : reg = cpu->c; break;
+ case REG_D : reg = cpu->d; break;
+ case REG_S : reg = cpu->s; break;
+ case REG_F : reg = cpu->f; break;
+ case REG_SP : reg = cpu->sp; break;
+ case REG_BP : reg = cpu->bp; break;
+ case REG_R11: reg = cpu->r11; break;
+ case REG_R12: reg = cpu->r12; break;
+ case REG_R13: reg = cpu->r13; break;
+ case REG_R14: reg = cpu->r14; break;
+ case REG_R15: reg = cpu->r15; break;
+ }
+ value[i] += reg;
+ }
+ if (op[i].id == MEM_SIB) {
+ value[i] *= op[i].scale+1;
+ }
+ #if getclk
+ cpu->clk += inc_clk;
+ #endif
+ }
+ }
+ }
+ return address;
+}
+
-static /*inline*/ uint64_t adc(struct sux *cpu, uint64_t reg, uint64_t value, uint8_t carry, uint8_t thread) {
+static /*inline*/ uint64_t adc(struct sux *cpu, uint64_t reg, uint64_t value, uint8_t carry, uint8_t size, uint8_t thread) {
+ size = (size > 8) ? 8 : size;
+ uint8_t msb = size*8;
uint64_t sum = reg+value+carry;
setflag(sum == 0, Z);
- setflag((sum >> 63), N);
- setflag(((reg^value) >> 63) && ((reg^sum) >> 63), V);
+ setflag(sum >> (msb-1), N);
+ setflag(((reg^value) >> (msb-1)) && ((reg^sum) >> (msb-1)), V);
setflag((sum < value), C);
return sum;
}
@@ -507,22 +605,28 @@ static /*inline*/ uint64_t pull(struct sux *cpu, uint8_t size, uint8_t thread) {
return value;
}
-static /*inline*/ uint64_t and(struct sux *cpu, uint64_t reg, uint64_t value, uint8_t thread) {
+static /*inline*/ uint64_t and(struct sux *cpu, uint64_t reg, uint64_t value, uint8_t size, uint8_t thread) {
+ size = (size > 8) ? 8 : size;
+ uint8_t msb = size*8;
reg &= value;
setflag(reg == 0, Z);
- setflag(reg >> 63, N);
+ setflag(reg >> (msb-1), N);
return reg;
}
-static /*inline*/ uint64_t or(struct sux *cpu, uint64_t reg, uint64_t value, uint8_t thread) {
+static /*inline*/ uint64_t or(struct sux *cpu, uint64_t reg, uint64_t value, uint8_t size, uint8_t thread) {
+ size = (size > 8) ? 8 : size;
+ uint8_t msb = size*8;
reg |= value;
setflag(reg == 0, Z);
- setflag(reg >> 63, N);
+ setflag(reg >> (msb-1), N);
return reg;
}
-static /*inline*/ uint64_t xor(struct sux *cpu, uint64_t reg, uint64_t value, uint8_t thread) {
+static /*inline*/ uint64_t xor(struct sux *cpu, uint64_t reg, uint64_t value, uint8_t size, uint8_t thread) {
+ size = (size > 8) ? 8 : size;
+ uint8_t msb = size*8;
reg ^= value;
setflag(reg == 0, Z);
- setflag(reg >> 63, N);
+ setflag(reg >> (msb-1), N);
return reg;
}
@@ -589,19 +693,23 @@ static /*inline*/ uint64_t ror(struct sux *cpu, uint64_t reg, uint64_t value, ui
return sum;
}
-static /*inline*/ uint64_t mul(struct sux *cpu, uint64_t reg, uint64_t value, uint8_t thread) {
+static /*inline*/ uint64_t mul(struct sux *cpu, uint64_t reg, uint64_t value, uint8_t size, uint8_t thread) {
+ size = (size > 8) ? 8 : size;
+ uint8_t msb = size*8;
uint64_t sum = reg*value;
setflag(sum == 0, Z);
- setflag(sum >> 63, N);
- setflag(!((reg^value) >> 63) && ((reg^sum) >> 63), V);
+ setflag(sum >> (msb-1), N);
+ setflag(!((reg^value) >> (msb-1)) && ((reg^sum) >> (msb-1)), V);
return sum;
}
-static /*inline*/ uint64_t divd(struct sux *cpu, uint64_t reg, uint64_t value, uint64_t *rem, uint8_t thread) {
+static /*inline*/ uint64_t divd(struct sux *cpu, uint64_t reg, uint64_t value, uint64_t *rem, uint8_t size, uint8_t thread) {
+ size = (size > 8) ? 8 : size;
+ uint8_t msb = size*8;
uint64_t sum = reg/value;
*rem = reg % value;
setflag(sum == 0, Z);
- setflag((sum >> 63), N);
+ setflag(sum >> (msb-1), N);
return sum;
}
@@ -726,6 +834,264 @@ static /*inline*/ void store(struct sux *cpu, uint64_t address, uint64_t reg, ui
write_value(cpu, reg, address, size, 1, 1);
}
+static /*inline*/ uint64_t mov(struct sux *cpu, uint64_t src, uint64_t size, uint8_t thread) {
+ size = (size > 7) ? 7 : size;
+ uint8_t msb = (size+1)*8;
+ uint64_t dst = 0;
+ uint64_t mask = (-(uint64_t)1 >> ((7 - size) * 8));
+ if (size < 7) {
+ dst = (dst & ~mask) | (src & mask);
+ } else {
+ dst = src;
+ }
+ setflag(dst == 0, Z);
+ setflag(dst >> (msb-1), N);
+ return dst;
+}
+
+static /*inline*/ uint64_t set(struct sux *cpu, uint8_t flag, uint8_t thread) {
+ return flag;
+}
+
+static /*inline*/ uint64_t inc_dec(struct sux *cpu, uint64_t value, uint8_t size, uint8_t inc, uint8_t thread) {
+ size = (size > 8) ? 8 : size;
+ uint8_t msb = size*8;
+ value += (inc) ? 1 : -1;
+ setflag(value == 0, Z);
+ setflag(value >> (msb-1), N);
+ return value;
+}
+
+static /*inline*/ uint64_t imul(struct sux *cpu, uint64_t dst, uint64_t value, uint8_t size, uint8_t thread) {
+ size = (size > 8) ? 8 : size;
+ uint8_t msb = size*8;
+ int64_t sum = dst*value;
+ setflag(sum == 0, Z);
+ setflag(sum >> (msb-1), N);
+ setflag(!((dst^value) >> (msb-1)) && ((dst^sum) >> (msb-1)), V);
+ return sum;
+}
+
+static /*inline*/ uint64_t idiv(struct sux *cpu, uint64_t dst, uint64_t value, uint64_t *rem, uint8_t size, uint8_t thread) {
+ size = (size > 8) ? 8 : size;
+ uint8_t msb = size*8;
+ int64_t sum = dst/value;
+ *rem = dst % value;
+ setflag(sum == 0, Z);
+ setflag(sum >> (msb-1), N);
+ return sum;
+}
+
+static /*inline*/ uint64_t neg(struct sux *cpu, uint64_t value, uint8_t size, uint8_t thread) {
+ size = (size > 8) ? 8 : size;
+ uint8_t msb = size*8;
+ value = -value;
+ setflag(value == 0, Z);
+ setflag(value >> (msb-1), N);
+ return value;
+}
+
+static /*inline*/ void exec_ortho_inst(struct sux *cpu, uint8_t opcode, uint8_t prefix, uint8_t size, uint8_t *op_type, uint8_t *op_id, uint8_t thread) {
+ uint64_t dst = 0;
+ uint64_t src = 0;
+ uint64_t rem = 0;
+ uint64_t address[2] = {0, 0};
+ int isdiv = 0;
+ operand op[2];
+ cpu->pc = get_ortho_addr(cpu, prefix, cpu->pc, op, address, op_type, op_id, 1, 1, thread);
+ if (op[1].type) {
+ src = read_value(cpu, 0, op[1].value, size, 1, 1);
+ } else {
+ switch (op[1].id) {
+ case REG_A : src = cpu->a; break;
+ case REG_B : src = cpu->b; break;
+ case REG_X : src = cpu->x; break;
+ case REG_Y : src = cpu->y; break;
+ case REG_E : src = cpu->e; break;
+ case REG_C : src = cpu->c; break;
+ case REG_D : src = cpu->d; break;
+ case REG_S : src = cpu->s; break;
+ case REG_F : src = cpu->f; break;
+ case REG_SP : src = cpu->sp; break;
+ case REG_BP : src = cpu->bp; break;
+ case REG_R11: src = cpu->r11; break;
+ case REG_R12: src = cpu->r12; break;
+ case REG_R13: src = cpu->r13; break;
+ case REG_R14: src = cpu->r14; break;
+ case REG_R15: src = cpu->r15; break;
+ }
+ }
+ if (op[0].type) {
+ dst = read_value(cpu, 0, op[0].value, size, 1, 1);
+ } else {
+ switch (op[0].id) {
+ case REG_A : dst = cpu->a; break;
+ case REG_B : dst = cpu->b; break;
+ case REG_X : dst = cpu->x; break;
+ case REG_Y : dst = cpu->y; break;
+ case REG_E : dst = cpu->e; break;
+ case REG_C : dst = cpu->c; break;
+ case REG_D : dst = cpu->d; break;
+ case REG_S : dst = cpu->s; break;
+ case REG_F : dst = cpu->f; break;
+ case REG_SP : dst = cpu->sp; break;
+ case REG_BP : dst = cpu->bp; break;
+ case REG_R11: dst = cpu->r11; break;
+ case REG_R12: dst = cpu->r12; break;
+ case REG_R13: dst = cpu->r13; break;
+ case REG_R14: dst = cpu->r14; break;
+ case REG_R15: dst = cpu->r15; break;
+ }
+ }
+ switch (opcode) {
+ case ORTHO_2OP(MNG):
+ if (getflag(N)) {
+ dst = mov(cpu, src, size, thread);
+ }
+ break;
+ case ORTHO_2OP(MPO):
+ if (!getflag(N)) {
+ dst = mov(cpu, src, size, thread);
+ }
+ break;
+ case ORTHO_2OP(MCS):
+ if (getflag(C)) {
+ dst = mov(cpu, src, size, thread);
+ }
+ break;
+ case ORTHO_2OP(MCC):
+ if (!getflag(C)) {
+ dst = mov(cpu, src, size, thread);
+ }
+ break;
+ case ORTHO_2OP(MEQ):
+ if (getflag(Z)) {
+ dst = mov(cpu, src, size, thread);
+ }
+ break;
+ case ORTHO_2OP(MNE):
+ if (!getflag(Z)) {
+ dst = mov(cpu, src, size, thread);
+ }
+ break;
+ case ORTHO_2OP(MVS):
+ if (getflag(V)) {
+ dst = mov(cpu, src, size, thread);
+ }
+ break;
+ case ORTHO_2OP(MVC):
+ if (!getflag(V)) {
+ dst = mov(cpu, src, size, thread);
+ }
+ break;
+ case ORTHO_2OP(MOV): dst = mov(cpu, src, size, thread); break;
+ case ORTHO_2OP(ADC): dst = adc(cpu, dst, src, getflag(C), (op[0].type) ? size+1 : 8, thread); break;
+ case ORTHO_2OP(SBC): dst = adc(cpu, dst, ~src, getflag(C), (op[0].type) ? size+1 : 8, thread); break;
+ case ORTHO_2OP(ADD): dst = adc(cpu, dst, src, 0, (op[0].type) ? size+1 : 8, thread); break;
+ case ORTHO_2OP(SUB): dst = adc(cpu, dst, ~src, 1, (op[0].type) ? size+1 : 8, thread); break;
+ case ORTHO_2OP(AND): dst = and(cpu, dst, src, (op[0].type) ? size+1 : 8, thread); break;
+ case ORTHO_2OP(OR ): dst = or(cpu, dst, src, (op[0].type) ? size+1 : 8, thread); break;
+ case ORTHO_2OP(XOR): dst = xor(cpu, dst, src, (op[0].type) ? size+1 : 8, thread); break;
+ case ORTHO_2OP(LSL): dst = lsl(cpu, dst, src, (op[0].type) ? size+1 : 8, thread); break;
+ case ORTHO_2OP(LSR): dst = lsr(cpu, dst, src, (op[0].type) ? size+1 : 8, thread); break;
+ case ORTHO_2OP(ROL): dst = rol(cpu, dst, src, (op[0].type) ? size+1 : 8, thread); break;
+ case ORTHO_2OP(ROR): dst = ror(cpu, dst, src, (op[0].type) ? size+1 : 8, thread); break;
+ case ORTHO_2OP(ASR): dst = asr(cpu, dst, src, (op[0].type) ? size+1 : 8, thread); break;
+ case ORTHO_2OP(MUL): dst = mul(cpu, dst, src, (op[0].type) ? size+1 : 8, thread); break;
+ case ORTHO_2OP(DIV): dst = divd(cpu, dst, src, &rem, (op[0].type) ? size+1 : 8, thread); isdiv = 1; break;
+ case ORTHO_2OP(CMP): adc(cpu, dst, ~src, 1, (op[0].type) ? size+1 : 8, thread); break;
+ case ORTHO_2OP(PCN): dst = popcnt(cpu, src, thread); break;
+ case ORTHO_2OP(IML): dst = imul(cpu, dst, src, (op[0].type) ? size+1 : 8, thread); break;
+ case ORTHO_2OP(IDV): dst = idiv(cpu, dst, src, &rem, (op[0].type) ? size+1 : 8, thread); isdiv = 1; break;
+ case ORTHO_2OP(LEA):
+ do {
+ uint64_t address;
+ uint64_t mask;
+ if (op[1].type) {
+ uint8_t addr_size = get_ortho_addrsize(prefix, op[1].id);
+ size = (!size) ? addr_size : size;
+ address = op[1].value;
+ } else {
+ address = src;
+ }
+ mask = (-(uint64_t)1 >> ((7 - size) * 8));
+ dst = (address & mask);
+ } while (0);
+ break;
+ case ORTHO_1OP(PEA):
+ do {
+ uint64_t address = (op[0].type) ? op[0].value : dst;
+ push(cpu, address, 7, thread);
+ } while (0);
+ break;
+ case ORTHO_1OP(INC): dst = inc_dec(cpu, dst, size, 1, thread); break;
+ case ORTHO_1OP(DEC): dst = inc_dec(cpu, dst, size, 0, thread); break;
+ case ORTHO_1OP(PSH): push(cpu, dst, size, thread); break;
+ case ORTHO_1OP(PUL): dst = pull(cpu, size, thread); break;
+ case ORTHO_1OP(NOT): dst = ~dst; break;
+ case ORTHO_1OP(CLZ): dst = lbcnt(cpu, src, 0, size, thread); break;
+ case ORTHO_1OP(CLO): dst = lbcnt(cpu, src, 1, size, thread); break;
+ case ORTHO_1OP(SWP): dst = swap(cpu, dst, size, thread); break;
+ case ORTHO_1OP(NEG): dst = neg(cpu, dst, size, thread); break;
+ case ORTHO_1CC(SET, NG): dst = set(cpu, getflag(N), thread); break;
+ case ORTHO_1CC(SET, PO): dst = set(cpu, !getflag(N), thread); break;
+ case ORTHO_1CC(SET, CS): dst = set(cpu, getflag(C), thread); break;
+ case ORTHO_1CC(SET, CC): dst = set(cpu, !getflag(C), thread); break;
+ case ORTHO_1CC(SET, EQ): dst = set(cpu, getflag(Z), thread); break;
+ case ORTHO_1CC(SET, NE): dst = set(cpu, !getflag(Z), thread); break;
+ case ORTHO_1CC(SET, VS): dst = set(cpu, getflag(V), thread); break;
+ case ORTHO_1CC(SET, VC): dst = set(cpu, !getflag(V), thread); break;
+
+ }
+
+ if (op[0].type) {
+ write_value(cpu, dst, op[0].value, size, 1, 1);
+ } else {
+ switch (op[0].id) {
+ case REG_A : cpu->a = dst; break;
+ case REG_B : cpu->b = dst; break;
+ case REG_X : cpu->x = dst; break;
+ case REG_Y : cpu->y = dst; break;
+ case REG_E : cpu->e = dst; break;
+ case REG_C : cpu->c = dst; break;
+ case REG_D : cpu->d = dst; break;
+ case REG_S : cpu->s = dst; break;
+ case REG_F : cpu->f = dst; break;
+ case REG_SP : cpu->sp = dst; break;
+ case REG_BP : cpu->bp = dst; break;
+ case REG_R11: cpu->r11 = dst; break;
+ case REG_R12: cpu->r12 = dst; break;
+ case REG_R13: cpu->r13 = dst; break;
+ case REG_R14: cpu->r14 = dst; break;
+ case REG_R15: cpu->r15 = dst; break;
+ }
+ }
+ if (isdiv) {
+ if (op[1].type) {
+ write_value(cpu, rem, op[1].value, size, 1, 1);
+ } else {
+ switch (op[1].id) {
+ case REG_A : cpu->a = rem; break;
+ case REG_B : cpu->b = rem; break;
+ case REG_X : cpu->x = rem; break;
+ case REG_Y : cpu->y = rem; break;
+ case REG_E : cpu->e = rem; break;
+ case REG_C : cpu->c = rem; break;
+ case REG_D : cpu->d = rem; break;
+ case REG_S : cpu->s = rem; break;
+ case REG_F : cpu->f = rem; break;
+ case REG_SP : cpu->sp = rem; break;
+ case REG_BP : cpu->bp = rem; break;
+ case REG_R11: cpu->r11 = rem; break;
+ case REG_R12: cpu->r12 = rem; break;
+ case REG_R13: cpu->r13 = rem; break;
+ case REG_R14: cpu->r14 = rem; break;
+ case REG_R15: cpu->r15 = rem; break;
+ }
+ }
+ }
+}
+
static /*inline*/ void exec_ext_inst(struct sux *cpu, uint8_t opcode, uint8_t prefix, uint64_t value, uint64_t address, uint8_t size, uint8_t thread) {
uint8_t addr_size = get_addrsize(prefix, ext_optype[opcode]);
uint8_t tmp = 0;
@@ -767,35 +1133,35 @@ static /*inline*/ void exec_ext_inst(struct sux *cpu, uint8_t opcode, uint8_t pr
case ADD_AB : /* ADD Absolute. */
case ADD_Z : /* ADD Zero Matrix. */
case ADD_E : /* ADD E Indirect. */
- cpu->a = adc(cpu, cpu->a, value, 0, thread);
+ cpu->a = adc(cpu, cpu->a, value, 0, 8, thread);
break;
case SUB_IMM: /* SUB Immediate. */
case SUB_AB : /* SUB Absolute. */
case SUB_Z : /* SUB Zero Matrix. */
case SUB_E : /* SUB E Indirect. */
- cpu->a = adc(cpu, cpu->a, ~value, 1, thread);
+ cpu->a = adc(cpu, cpu->a, ~value, 1, 8, thread);
break;
case ADE_IMM: /* ADE Immediate. */
case ADE_AB : /* ADE Absolute. */
case ADE_Z : /* ADE Zero Matrix. */
- cpu->e = adc(cpu, cpu->e, value, 0, thread);
+ cpu->e = adc(cpu, cpu->e, value, 0, 8, thread);
break;
case SBE_IMM: /* SBE Immediate. */
case SBE_AB : /* SBE Absolute. */
case SBE_Z : /* SBE Zero Matrix. */
- cpu->e = adc(cpu, cpu->e, ~value, 1, thread);
+ cpu->e = adc(cpu, cpu->e, ~value, 1, 8, thread);
break;
case ADS_IMM: /* ADS Immediate. */
case ADS_AB : /* ADS Absolute. */
case ADS_Z : /* ADS Zero Matrix. */
case ADS_E : /* ADS E Indirect. */
- cpu->sp = adc(cpu, cpu->sp, value, 0, thread);
+ cpu->sp = adc(cpu, cpu->sp, value, 0, 8, thread);
break;
case SBS_IMM: /* SBS Immediate. */
case SBS_AB : /* SBS Absolute. */
case SBS_Z : /* SBS Zero Matrix. */
case SBS_E : /* SBS E Indirect. */
- cpu->sp = adc(cpu, cpu->sp, ~value, 1, thread);
+ cpu->sp = adc(cpu, cpu->sp, ~value, 1, 8, thread);
break;
case NOT_A : /* NOT Accumulator. */
cpu->a = ~cpu->a;
@@ -844,7 +1210,7 @@ static /*inline*/ void exec_ext_inst(struct sux *cpu, uint8_t opcode, uint8_t pr
case CPE_IMM: /* CPE Immediate. */
case CPE_AB : /* CPE Absolute. */
case CPE_Z : /* CPE Zero Matrix. */
- adc(cpu, cpu->e, ~value, 1, thread);
+ adc(cpu, cpu->e, ~value, 1, 8, thread);
break;
case ICE_AB : /* ICE Absolute. */
case ICE_Z : /* ICE Zero Matrix. */
@@ -1014,7 +1380,7 @@ static /*inline*/ void exec_base_inst(struct sux *cpu, uint8_t opcode, uint8_t p
case ADC_IMM: /* ADC Immediate. */
case ADC_AB: /* ADC Absolute. */
case ADC_Z: /* ADC Zero Matrix. */
- cpu->a = adc(cpu, cpu->a, value, getflag(C), thread);
+ cpu->a = adc(cpu, cpu->a, value, 8, getflag(C), thread);
break;
case PHP_IMP: push(cpu, cpu->ps.u8[thread], 0, thread); break; /* PusH Processor status to stack. */
case PHA_IMP: push(cpu, cpu->a , size, thread); break; /* PusH Accumulator to stack. */
@@ -1042,7 +1408,7 @@ static /*inline*/ void exec_base_inst(struct sux *cpu, uint8_t opcode, uint8_t p
case SBC_IMM: /* SBC Immediate. */
case SBC_AB: /* SBC Absolute. */
case SBC_Z: /* SBC Zero Matrix. */
- cpu->a = adc(cpu, cpu->a, ~value, getflag(C), thread);
+ cpu->a = adc(cpu, cpu->a, ~value, 8, getflag(C), thread);
break;
case PLP_IMP: cpu->ps.u8[thread] = pull(cpu, 0, thread); break; /* PuLl Processor status from stack. */
case PLA_IMP: cpu->a = pull(cpu, size, thread); break; /* PuLl Accumulator from stack. */
@@ -1055,7 +1421,7 @@ static /*inline*/ void exec_base_inst(struct sux *cpu, uint8_t opcode, uint8_t p
case AND_IMM: /* AND Immediate. */
case AND_AB: /* AND Absolute. */
case AND_Z: /* AND Zero Matrix. */
- cpu->a = and(cpu, cpu->a, value, thread);
+ cpu->a = and(cpu, cpu->a, value, 8, thread);
break;
case BPO_REL: /* BPO Relative. */
if (!getflag(N)) {
@@ -1067,7 +1433,7 @@ static /*inline*/ void exec_base_inst(struct sux *cpu, uint8_t opcode, uint8_t p
case ORA_IMM: /* ORA Immediate. */
case ORA_AB: /* ORA Absolute. */
case ORA_Z: /* ORA Zero Matrix. */
- cpu->a = or(cpu, cpu->a, value, thread);
+ cpu->a = or(cpu, cpu->a, value, 8, thread);
break;
case SEI_IMP: /* SEt Interrupt. */
setflag(1, I);
@@ -1082,7 +1448,7 @@ static /*inline*/ void exec_base_inst(struct sux *cpu, uint8_t opcode, uint8_t p
case XOR_IMM: /* XOR Immediate. */
case XOR_AB: /* XOR Absolute. */
case XOR_Z: /* XOR Zero Matrix. */
- cpu->a = xor(cpu, cpu->a, value, thread);
+ cpu->a = xor(cpu, cpu->a, value, 8, thread);
break;
case CLI_IMP: /* CLear Interrupt. */
setflag(0, I);
@@ -1218,7 +1584,7 @@ static /*inline*/ void exec_base_inst(struct sux *cpu, uint8_t opcode, uint8_t p
case MUL_IMM: /* MUL Immediate. */
case MUL_AB: /* MUL Absolute. */
case MUL_Z: /* MUL Zero Matrix. */
- cpu->a = mul(cpu, cpu->a, value, thread);
+ cpu->a = mul(cpu, cpu->a, value, 8, thread);
break;
case BVC_REL: /* BVC Relative. */
if (!getflag(V)) {
@@ -1230,7 +1596,7 @@ static /*inline*/ void exec_base_inst(struct sux *cpu, uint8_t opcode, uint8_t p
case DIV_AB: /* DIV Absolute. */
case DIV_Z: /* DIV Zero Matrix. */
rem = (opcode != DIV_B) ? &cpu->b : &cpu->x;
- cpu->a = divd(cpu, cpu->a, value, rem, thread);
+ cpu->a = divd(cpu, cpu->a, value, rem, 8, thread);
break;
case CLV_IMP: /* CLear oVerflow flag. */
setflag(0, V);
@@ -1241,7 +1607,7 @@ static /*inline*/ void exec_base_inst(struct sux *cpu, uint8_t opcode, uint8_t p
case CPB_IN: /* CPB Indirect. */
case CPB_IX: /* CPB Indexed Indirect. */
case CPB_IY: /* CPB Indirect Indexed. */
- adc(cpu, cpu->b, ~value, 1, thread);
+ adc(cpu, cpu->b, ~value, 1, 8, thread);
break;
case CMP_B: /* CMP B register. */
value = cpu->b; /* Falls Through. */
@@ -1251,17 +1617,17 @@ static /*inline*/ void exec_base_inst(struct sux *cpu, uint8_t opcode, uint8_t p
case CMP_IN: /* CMP Indirect. */
case CMP_IX: /* CMP Indexed Indirect. */
case CMP_IY: /* CMP Indirect Indexed. */
- adc(cpu, cpu->a, ~value, 1, thread);
+ adc(cpu, cpu->a, ~value, 1, 8, thread);
break;
case CPY_IMM: /* CPY Immediate. */
case CPY_AB: /* CPY Absolute. */
case CPY_Z: /* CPY Zero Matrix. */
- adc(cpu, cpu->y, ~value, 1, thread);
+ adc(cpu, cpu->y, ~value, 1, 8, thread);
break;
case CPX_IMM: /* CPX Immediate. */
case CPX_AB: /* CPX Absolute. */
case CPX_Z: /* CPX Zero Matrix. */
- adc(cpu, cpu->x, ~value, 1, thread);
+ adc(cpu, cpu->x, ~value, 1, 8, thread);
break;
case INC_IMP: cpu->a = idr(cpu, cpu->a, 1, thread); break;
case INB_IMP: cpu->b = idr(cpu, cpu->b, 1, thread); break;
@@ -1315,3 +1681,7 @@ static /*inline*/ void exec_base_inst(struct sux *cpu, uint8_t opcode, uint8_t p
break;
}
}
+
+#undef ORTHO_1CC
+#undef ORTHO_1OP
+#undef ORTHO_2OP
generated by cgit v1.2.3-13-gbd6f (git 2.30.0) at 2024-12-26 05:20:05 +0000