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2020-12-09- Implemented support for the `set` instruction in themrb0nk500
assembler. The main thing I had to do was implement the parsing of the condition code token, but that wasn't hard to do, since I had already done the lexing part already. The next thing to do, will be to design a calling convention for Sux.
2020-12-08- Implemented support for the Orthogonal extension intomrb0nk500
both the assembler, and the emulator. I finally figured out how I could get support for the Ortho extension implemented into the old assembler. The only reason for doing this, is to buy me some while I start work on the new assembler, and to help me get an idea for how to do the same in the new assembler.
2020-11-20- Implemented support for Sux's base extension.mrb0nk500
This is the biggest milestone I've reached for this project, since the base extension changes alot about what Sux can do by default, and now makes it a viable instruction set for modern day use, when compared with other instruction sets.
2020-08-08- Refactored the opcode table, in order to make themrb0nk500
instruction formatting simpler. - Refactored the instruction table of the emulator's assembler, it now has two parts, the addressing mode bits, and the base value. The base value is what's used to generate the actual opcode, with the addressing mode bits telling the assembler what addressing modes this instruction supports. The reason for doing this was to use less space. For comparison, the previous version used 870 bytes for the instruction table, while the new version uses only 222 bytes. The new version is nearly 4 times smaller than the pervious version. - The B register based ALU instructions now use their own addressing mode, and are specified by using 'b' as the operand for those instructions. For example, to add the Accumulator with the B register, you now use "ADC B" instead of "AAB".
2020-07-06- Implemented a new opcode table.mrb0nk500
- Added a new preifx called the OF prefix, which adds the contents of a specific register to the current operand. - Added a table generator, which parses opcode table csv files.
2020-05-29Make JSL, JSR absolute, and remove RTL.mrb0nk500
The reason for doing this was because JSL, and RTL are redundent, as they both do the same thing as JSR, and RTS.
2020-05-03Put the instruction, and I/O routines into separatemrb0nk500
functions. I did this to make it more readable, while still making it fast, due to inlining it.