cisc-0.2 - An emulator for the Sux instruction set.

Age	Commit message (Collapse)	Author
2019-11-30	Start work on rev2 of Sux.	mrb0nk500
	Added a prefix byte to tell the CPU certain information such as, how many bytes to load into the registers, or what ISA extension we want to use. I also added an assembly language monitor, so that I don't have to write stuff in machine code.
2019-11-26	rev1 of Sux has been completed!rev1	mrb0nk500
	I have now implemented BRK, and RTI. Also, BieHDC, and I will both be working on rev2.
2019-11-26	Revamped the entire emulator.	mrb0nk500
	I finally implemented the other addressing modes, and added a Makefile. Not sure when I will start work on rev2 of Sux, but it will be sometime soon.
2019-11-20	Fixed some bugs in some instructions.	mrb0nk500
	Fixed stack based instructions. Fixed the rotate instructions. Added carry to the shift instructions.
2019-11-17	The emulator is working!!!	mrb0nk500

2019-11-16	Implemented memory based instructions, and removed	mrb0nk500
	some unneeded instructions.
2019-11-13	Actually set the Processor Status flags correctly, and	mrb0nk500
	revamp some other stuff.
2019-11-11	Started work on simultanious multithreading, and branching.	mrb0nk500

2019-11-11	Added more instructions to the ALU.	mrb0nk500

2019-11-11	Added comments in opcode.h, and started work on the	mrb0nk500
	Sux emulator.