From f478e6c1223cc8370fa51d44b9244ec25be99788 Mon Sep 17 00:00:00 2001
From: mrb0nk500 <b0nk@b0nk.xyz>
Date: Sun, 13 Feb 2022 20:20:59 -0400
Subject: igen: Start work on writing an instruction handler generator.

This will make it easier in the long run to modify
instructions, add new instructions, and move the opcode
tables around.
---
 igen/sux-igen/addr-modes.igen | 91 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 91 insertions(+)
 create mode 100644 igen/sux-igen/addr-modes.igen

(limited to 'igen/sux-igen/addr-modes.igen')

diff --git a/igen/sux-igen/addr-modes.igen b/igen/sux-igen/addr-modes.igen
new file mode 100644
index 0000000..3780ed2
--- /dev/null
+++ b/igen/sux-igen/addr-modes.igen
@@ -0,0 +1,91 @@
+#include "utils.igen"
+
+%%
+
+/*
+am((abs|zm)[xy]?) {
+	if (am == zmx || am == absx) {
+		idx = cpu->x;
+	} else if (am == zmy || am == absy) {
+		idx = cpu->y;
+	}
+
+	if (am == abs || am == absx || am == absy) {
+		is_abs = 1;
+	}
+
+	size = ((prefix & 0xC) >> 1) | is_abs;
+	addr = read(cpu->pc, size) + idx;
+	value = read(addr, rs);
+}
+
+am((a)?ind([xy])?) {
+	if (am == indx || am == aindx) {
+		idx = cpu->x;
+		pre_idx = 1;
+	} else if (am == indy || am == aindy) {
+		idx = cpu->y;
+	}
+
+	if (am == aind || am == aindx || am == aindy) {
+		is_abs = 1;
+	}
+
+	size = ((prefix & 0xC) >> 1) | is_abs;
+
+	if (pre_idx) {
+		addr = read(read(cpu->pc + idx, size), 7);
+	} else {
+		addr = read(read(cpu->pc, size), 7) + idx;
+	}
+
+	value = read(addr, rs);
+}
+
+am(eind) {
+	addr = cpu->e;
+	value = read(addr, rs);
+}
+*/
+
+am(abs|zm([xy])?) {
+	if (am == abs) {
+		mem_type = ABS;
+	} else {
+		if (am == zmx) {
+			idx = cpu->x;
+		} else if (am == zmy) {
+			idx = cpu->y;
+		}
+		mem_type = ZM;
+	}
+	addr = read_addr(prefix, mem_type) + idx;
+	value = read(addr, rs);
+}
+
+am(ind([xy])?) {
+	if (am == indx) {
+		idx = cpu->x;
+		pre_idx = 1;
+	} else if (am == indy) {
+		idx = cpu->y;
+	}
+	mem_type = ZM;
+	addr = ind_idx_addr(prefix, mem_type, idx, pre_idx);
+	value = read(addr, rs);
+}
+
+am(rel) {
+	addr = rel_addr(prefix);
+}
+
+am(imm) {
+	value = read(cpu->pc, rs);
+	cpu->pc += rs+1;
+}
+
+am(breg) {
+	value = cpu->b;
+}
+
+%%
-- 
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