From f478e6c1223cc8370fa51d44b9244ec25be99788 Mon Sep 17 00:00:00 2001
From: mrb0nk500 <b0nk@b0nk.xyz>
Date: Sun, 13 Feb 2022 20:20:59 -0400
Subject: igen: Start work on writing an instruction handler generator.

This will make it easier in the long run to modify
instructions, add new instructions, and move the opcode
tables around.
---
 igen/sux-igen/utils.igen | 50 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)
 create mode 100644 igen/sux-igen/utils.igen

(limited to 'igen/sux-igen/utils.igen')

diff --git a/igen/sux-igen/utils.igen b/igen/sux-igen/utils.igen
new file mode 100644
index 0000000..7385117
--- /dev/null
+++ b/igen/sux-igen/utils.igen
@@ -0,0 +1,50 @@
+update_flags_nz(value) {
+	cpu->ps.N = bit(value, msb-1);
+	cpu->ps.Z = value == 0;
+}
+
+get_flag(name, match, flag) {
+	if (name == match) {
+		return flag;
+	} else {
+		return !flag;
+	}
+}
+
+jump(addr, fallback, flag) {
+	if (flag) {
+		return addr;
+	} else {
+		return fallback;
+	}
+}
+
+read(addr, size) {
+	return read_value(addr, size);
+}
+
+write(value, addr, size) {
+	write_value(value, addr, size);
+}
+
+adc(a, b, carry) {
+	sum = a + b + carry;
+	update_flags_nz(sum);
+	cpu->ps.C = sum < b;
+	cpu->ps.V = bit(a^b, msb-1) && bit(a^sum, msb-1);
+	return sum;
+}
+
+mul(a, b) {
+	sum = a * b;
+	update_flags_nz(sum);
+	cpu->ps.V = bit(a^b, msb-1) && bit(a^sum, msb-1);
+	return sum;
+}
+
+div(a, b, *rem) {
+	sum = a / b;
+	*rem = a % b;
+	update_flags_nz(sum);
+	return sum;
+}
-- 
cgit v1.2.3-13-gbd6f