From dc7ebb9d424bb39d59f09b8498746beb871c46f4 Mon Sep 17 00:00:00 2001 From: mrb0nk500 Date: Fri, 20 Nov 2020 11:50:47 -0500 Subject: - Cleaned up a bit of the code. - Made the debug print for the CPU flags more readable. - Started work on implementing line number support into SuBAsm. --- sux.c | 149 +++++++++++++++++++++--------------------------------------------- 1 file changed, 47 insertions(+), 102 deletions(-) (limited to 'sux.c') diff --git a/sux.c b/sux.c index adca16f..f064cee 100644 --- a/sux.c +++ b/sux.c @@ -1,4 +1,5 @@ #include "sux.h" +/*#include "microcode.h"*/ #include #if getclk @@ -44,101 +45,8 @@ struct suxthr { #if bench double ipc; -#endif -inline uint8_t get_addrsize(uint8_t prefix, uint8_t addrmode) { - uint8_t id = (prefix & 0x0C) >> 2; - switch (addrmode) { - case ZM: - switch (id) { - case 2: return 5; - case 3: return 3; - case 1: return 2; - case 0: return 0; - } - break; - case ABS: - switch (id) { - case 3: return 7; - case 2: return 6; - case 1: return 4; - case 0: return 1; - } - break; - } - return 0; -} -static inline uint8_t isrw(uint8_t opcode) { - switch (opcode) { - case STA_AB: /* STA Absolute. */ - case STA_Z: /* STA Zero Matrix. */ - case STA_ZX: /* STA Zero Matrix, Indexed with X. */ - case STA_ZY: /* STA Zero Matrix, Indexed with Y. */ - case STA_IN: /* STA Indirect. */ - case STA_IX: /* STA Indexed Indirect. */ - case STA_IY: /* STA Indirect Indexed. */ - case STY_AB: /* STY Absolute. */ - case STY_Z: /* STY Zero Matrix. */ - case STY_IN: /* STY Indirect. */ - case STX_AB: /* STX Absolute. */ - case STX_Z: /* STX Zero Matrix. */ - case STX_IN: /* STX Indirect. */ - case STB_AB: /* STB Absolute. */ - case STB_Z: /* STB Zero Matrix. */ - case STB_ZX: /* STB Zero Matrix, Indexed with X. */ - case STB_ZY: /* STB Zero Matrix, Indexed with Y. */ - case STB_IN: /* STB Indirect. */ - case STB_IX: /* STB Indexed Indirect. */ - case STB_IY: /* STB Indirect Indexed. */ - case INC_AB: /* INC Absolute. */ - case INC_Z: /* INC Zero Matrix. */ - case DEC_AB: /* DEC Absolute. */ - case DEC_Z: /* DEC Zero Matrix. */ - return 0; /* Writing. */ - default: - return 1; /* Reading. */ - } -} -static inline uint8_t isread(uint8_t opcode) { - switch (opcode) { - case LDA_IMM: /* LDA Immediate. */ - case LDA_AB: /* LDA Absolute. */ - case LDA_Z: /* LDA Zero Matrix. */ - case LDA_ZX: /* LDA Zero Matrix, Indexed with X. */ - case LDA_ZY: /* LDA Zero Matrix, Indexed with Y. */ - case LDA_IN: /* LDA Indirect. */ - case LDA_IX: /* LDA Indexed Indirect. */ - case LDA_IY: /* LDA Indirect Indexed. */ - case LDB_IMM: /* LDB Immediate. */ - case LDB_AB: /* LDB Absolute. */ - case LDB_Z: /* LDB Zero Matrix. */ - case LDB_ZX: /* LDB Zero Matrix, Indexed with X. */ - case LDB_ZY: /* LDB Zero Matrix, Indexed with Y. */ - case LDB_IN: /* LDB Indirect. */ - case LDB_IX: /* LDB Indexed Indirect. */ - case LDB_IY: /* LDB Indirect Indexed. */ - case LDY_IMM: /* LDY Immediate. */ - case LDY_AB: /* LDY Absolute. */ - case LDY_Z: /* LDY Zero Matrix. */ - case LDY_IN: /* LDY Indirect. */ - case LDX_IMM: /* LDX Immediate. */ - case LDX_AB: /* LDX Absolute. */ - case LDX_Z: /* LDX Zero Matrix. */ - case LDX_IN: /* LDX Indirect. */ - case JMP_AB: /* JMP Absolute. */ - case JMP_Z: /* JMP Zero Matrix. */ - case JMP_IN: /* JMP Indirect. */ - case JSR_IN: /* JSR Indirect. */ - case JSR_AB: /* Jump to SubRoutine. */ - case JSR_Z: /* JSR Zero Matrix. */ - return 0; - default: - return 1; - } -} - -#if bench void stop_timer() { time_done = 1; } @@ -195,6 +103,21 @@ void *run(void *args) { #if bench start_timer(1, 0); #endif + /*ucode uc; + uc.upc = 0; + uc.usp = 0xFF; + uc.alu_a = 0; + uc.alu_b = 0; + uc.dbus = 0; + for (int i = 0; i < AGU_IDX_CNT; uc.agu_idx[i++] = 0); + uc.agu_dben = 0; + uc.agu_oplen = 0; + uc.mdr = 0; + uc.mar = 0; + uc.ir = 0; + uc.itr = 0; + uc.clk = 0; + struct sux uc_test;*/ for (;;) { #if !bench if (end) { @@ -248,6 +171,7 @@ void *run(void *args) { value.u64 = read_value(cpu, 0, address.u64, size, 1, check_io); } } + /*decode_microinst(&uc, &uc_test, prefix, 0);*/ switch (opcode) { case CPS_IMP: /* Clear Processor Status. */ cpu->ps.u64 = 0; @@ -654,6 +578,35 @@ int main(int argc, char **argv) { int result; uint16_t vec = 0xFFC0; uint8_t offset; + /*for (int i = 0; i < 4096; i++) { + for (int j = 0; j < RW_UNITS; j++) { + mucode[i].ui.ru[j].type = rand(); + mucode[i].ui.wu[j].type = rand(); + } + mucode[i].ui.imm = rand(); + + mucode[i].ui.agu_sig.prefix = rand(); + mucode[i].ui.agu_sig.ind = rand(); + mucode[i].ui.agu_sig.ind_type = rand(); + mucode[i].ui.agu_sig.zm = rand(); + mucode[i].ui.agu_sig.idx_sub = rand(); + + mucode[i].ui.sig.mread = rand(); + mucode[i].ui.sig.mwrite = rand(); + mucode[i].ui.sig.inv_b = rand(); + mucode[i].ui.sig.c_in = rand(); + mucode[i].ui.sig.fetch = rand(); + mucode[i].ui.sig.set_nvzc = rand(); + mucode[i].ui.sig.rw_en = rand(); + + mucode[i].ui.is_jmp = rand(); + mucode[i].ui.jmp_type = rand(); + mucode[i].ui.cond_type = rand(); + mucode[i].ui.cond_reg = rand(); + mucode[i].ui.jmp_addr = rand(); + + for (int j = 0; j < sizeof(uinst); mucode[i].u8[j++] = (uint8_t)rand()); + }*/ for (int i = 0; i < THREADS; i++) { thr[i].sx.sp = (i << 16) | 0xFFFF; offset = (i) ? ((i-1) << 3) : 0; @@ -662,15 +615,7 @@ int main(int argc, char **argv) { thr[i].sx.b = 0; thr[i].sx.x = 0; thr[i].sx.y = 0; - thr[i].sx.pc = (uint64_t)addr[vec+0+offset] - | (uint64_t)addr[vec+1+offset] << 8 - | (uint64_t)addr[vec+2+offset] << 16 - | (uint64_t)addr[vec+3+offset] << 24 - | (uint64_t)addr[vec+4+offset] << 32 - | (uint64_t)addr[vec+5+offset] << 40 - | (uint64_t)addr[vec+6+offset] << 48 - | (uint64_t)addr[vec+7+offset] << 56; - + thr[i].sx.pc = read_value(&thr[i].sx, 0, vec+offset, 7, 0, 0); thr[i].th = i; #if !IO inst[i] = 0; -- cgit v1.2.3-13-gbd6f