#include <inttypes.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>

#define bench 0
#define debug 0
#define IO 1
#define getclk 0
#define keypoll 0

#define CPS	0x00 /* Clear Processor Status. */
#define ADC	0x01 /* ADd with Carry. */
#define AAB	0x02 /* Add Accumulator with carry by B register. */
#define ADC_AB	0x04 /* ADC Absolute. */
#define LDA_IN	0x05 /* LDA Indirect. */
#define ADC_Z	0x06 /* ADC Zero Matrix. */
#define PHP	0x08 /* PusH Processor status to stack. */
#define CPB	0x09 /* ComPare B register. */
#define PHB	0x0A /* PusH B register to stack. */
#define DEC_AB	0x0C /* DEC Absolute. */
#define DEC_Z	0x0D /* DEC Zero Matrix. */
#define JMP_Z	0x0E /* JuMP to memory location. */
#define JMP	0x10 /* JMP Absolute. */
#define SBC	0x11 /* SuBtract with Carry. */
#define SAB	0x12 /* Subtract Accumulator with carry by B register. */
#define SBC_AB	0x14 /* SBC Absolute. */
#define STA_IN	0x15 /* STA Indirect. */
#define SBC_Z	0x16 /* SBC Zero Matrix. */
#define ENT	0x18 /* ENd Threads. */
#define CPY	0x19 /* ComPare Y register. */
#define PLB	0x1A /* PuLl B register to stack. */
#define INC_AB	0x1C /* INC Absolute. */
#define INC_Z	0x1D /* INC Zero Matrix. */
#define JSR	0x1E /* Jump to SubRoutine. */
#define JSL	0x20 /* Jump to Subroutine Long. */
#define AND	0x21 /* bitwise AND with accumulator. */
#define ABA	0x22 /* bitwise And with Accumulator, and B register. */
#define AND_AB	0x24 /* AND Absolute. */
#define CMP_IN	0x25 /* CMP Indirect. */
#define AND_Z	0x26 /* AND Zero Matrix. */
#define PLP	0x28 /* PuLl Processor status from stack. */
#define CPX	0x29 /* ComPare X register. */
#define PHY	0x2A /* PusH Y register to stack. */
#define CPB_AB	0x2C /* CPB Absolute. */
#define CPB_Z	0x2D /* CPB Zero Matrix. */
#define BPO_Z	0x2E /* Branch if POsitive. */
#define BPO	0x30 /* BPO Absolute. */
#define ORA	0x31 /* bitwise OR with Accumulator. */
#define OAB	0x32 /* bitwise Or with Accumulator, and B register. */
#define ORA_AB	0x34 /* ORA Absolute. */
#define LDB_IN	0x35 /* LDB Indirect. */
#define ORA_Z	0x36 /* ORA Zero Matrix. */
#define STT	0x38 /* STart Threads. */
#define LDA_ZY	0x39 /* LDA Zero Matrix, indexed with Y. */
#define PLY	0x3A /* PuLl Y register from stack. */
#define CPX_AB	0x3C /* CPX Absolute. */
#define CPY_Z	0x3D /* CPY Zero Matrix. */
#define BNG_Z	0x3E /* Branch if NeGative. */
#define BNG	0x40 /* BNG Absolute. */
#define XOR	0x41 /* bitwise XOR with accumulator. */
#define XAB	0x42 /* bitwise Xor with Accumulator, and B register. */
#define XOR_AB	0x44 /* XOR Absolute. */
#define STB_IN	0x45 /* STB Indirect. */
#define XOR_Z	0x46 /* XOR Zero Matrix. */
#define PHA	0x48 /* PusH Accumulator to stack. */
#define STA_ZY	0x49 /* STA Zero Matrix, indexed with Y. */
#define PHX	0x4A /* PusH X register to stack. */
#define CPY_AB	0x4C /* CPY Absolute. */
#define CPX_Z	0x4D /* CPX Zero Matrix. */
#define BCS_Z	0x4E /* Branch if Carry Set. */
#define BCS	0x50 /* BCS Absolute. */
#define LSL	0x51 /* Logical Shift Left. */
#define LLB	0x52 /* Logical shift Left accumulator by B. */
#define LSL_AB	0x54 /* LSL Absolute. */
#define CPB_IN	0x55 /* CPB Indirect. */
#define LSL_Z	0x56 /* LSL Zero Matrix. */
#define CLC	0x58 /* CLear Carry flag. */
#define LDB_ZY	0x59 /* LDB Zero Matrix, indexed with Y. */
#define PLX	0x5A /* PuLl X register from stack. */
#define LDA_IY	0x5C /* LDA Indirect Indexed. */
#define LDA_IX	0x5D /* LDA Indexed Indirect. */
#define BCC_Z	0x5E /* Branch if Carry Clear. */
#define BCC	0x60 /* BCC Absolute. */
#define LSR	0x61 /* Logical Shift Right. */
#define LRB	0x62 /* Logical shift Right accumulator by B. */
#define LSR_AB	0x64 /* LSR Absolute. */
#define LDY_IN	0x65 /* LDY Indirect. */
#define LSR_Z	0x66 /* LSR Zero Matrix. */
#define PLA	0x68 /* PuLl Accumulator from stack. */
#define STB_ZY	0x69 /* STB Zero Matrix, indexed with Y. */
#define TAB	0x6A /* Transfer Accumulator to B.  */
#define STA_IY	0x6C /* STA Indirect Indexed. */
#define STA_IX	0x6D /* STA Indexed Indirect. */
#define BEQ_Z	0x6E /* Branch if EQual. */
#define BEQ	0x70 /* BEQ Absolute. */
#define ROL	0x71 /* ROtate Left. */
#define RLB	0x72 /* Rotate Left accumulator by B. */
#define ROL_AB	0x74 /* ROL Absolute. */
#define STY_IN	0x75 /* STY Indirect. */
#define ROL_Z	0x76 /* ROL Zero Matrix. */
#define SEC	0x78 /* SEt Carry flag. */
#define LDA_ZX	0x79 /* LDA Zero Matrix, indexed with X. */
#define TBA	0x7A /* Transfer B to Accumulator.  */
#define CMP_IY	0x7C /* CMP Indirect Indexed. */
#define CMP_IX	0x7D /* CMP Indexed Indirect. */
#define BNE_Z	0x7E /* Branch if Not Equal. */
#define BNE	0x80 /* BNE Absolute. */
#define ROR	0x81 /* ROtate Right. */
#define RRB	0x82 /* Rotate Right accumulator by B. */
#define ROR_AB	0x84 /* ROR Absolute. */
#define CPY_IN	0x85 /* CPY Indirect. */
#define ROR_Z	0x86 /* ROR Zero Matrix. */
#define DEY	0x88 /* DEcrement Y register. */
#define STA_ZX	0x89 /* STA Zero Matrix, indexed with X. */
#define TAY	0x8A /* Transfer Accumulator to Y. */
#define LDB_IY	0x8C /* LDB Indirect Indexed. */
#define LDB_IX	0x8D /* LDB Indexed Indirect. */
#define BVS_Z	0x8E /* Branch if oVerflow Set. */
#define BVS	0x90 /* BVS Absolute. */
#define MUL	0x91 /* MULtiply accumulator. */
#define MAB	0x92 /* Multiply Accumulator by B. */
#define MUL_AB	0x94 /* MUL Absolute. */
#define LDX_IN	0x95 /* LDX Indirect. */
#define MUL_Z	0x96 /* MUL Zero Matrix. */
#define CLI	0x98 /* CLear Interupt flag. */
#define LDB_ZX	0x99 /* LDB Zero Matrix, indexed with X. */
#define TYA	0x9A /* Transfer Y to Accumulator. */
#define STB_IY	0x9C /* STB Indirect Indexed. */
#define STB_IX	0x9D /* STB Indexed Indirect. */
#define BVC_Z	0x9E /* Branch if oVerflow Clear. */
#define BVC	0xA0 /* BVC Absolute. */
#define DIV	0xA1 /* DIVide with accumulator. */
#define DAB	0xA2 /* Divide Accumulator by B. */
#define DIV_AB	0xA4 /* DIV Absolute. */
#define STX_IN	0xA5 /* STX Indirect. */
#define DIV_Z	0xA6 /* DIV Zero Matrix. */
#define INY	0xA8 /* INcrement Y register. */
#define STB_ZX	0xA9 /* STB Zero Matrix, indexed with X. */
#define TAX	0xAA /* Transfer Accumulator to X. */
#define CPB_IY	0xAC /* CPB Indirect Indexed. */
#define CPB_IX	0xAD /* CPB Indexed Indirect. */
#define RTS	0xAE /* ReTurn from Subroutine. */
#define RTL	0xB0 /* ReTurn from subroutine Long. */
#define CMP	0xB1 /* CoMPare accumulator. */
#define CAB	0xB2 /* Compare Accumulator, and B. */
#define CMP_AB	0xB4 /* CMP Absolute. */
#define CPX_IN	0xB5 /* CPX Indirect. */
#define CMP_Z	0xB6 /* CMP Zero Matrix. */
#define SEI	0xB8 /* SEt Interupt flag. */
#define LDX	0xB9 /* LoaD X register. */
#define TXA	0xBA /* Transfer X to Accumulator. */
#define LDX_AB	0xBC /* LDX Absolute. */
#define LDX_Z	0xBD /* LDX Zero Matrix. */
#define JSR_IN	0xBE /* JSR Indirect. */
#define RTI	0xC0 /* ReTurn from Interrupt. */
#define LDA	0xC1 /* LoaD Accumulator. */
#define LDA_AB	0xC4 /* LDA Absolute. */
#define DEX	0xC5 /* DEcrement X register. */
#define LDA_Z	0xC6 /* LDA Zero Matrix. */
#define CLV	0xC8 /* CLear oVerflow flag. */
#define LDX_ZY	0xC9 /* LDX Zero Matrix, indexed with Y. */
#define TYX	0xCA /* Transfer Y to X. */
#define STA	0xCC /* STA Absolute. */
#define STA_Z	0xCD /* STore Accumulator. */
#define JMP_IN	0xCE /* JMP Indirect. */
#define TSX	0xD0 /* Transfer Stack pointer to X. */
#define LDB	0xD1 /* LoaD B register. */
#define LDB_AB	0xD4 /* LDB Absolute. */
#define INX	0xD5 /* INcrement X register. */
#define LDB_Z	0xD6 /* LDB Zero Matrix. */
#define WAI	0xD8 /* WAit for Interrupt. */
#define STX_ZY	0xD9 /* STX Zero Matrix, indexed with Y. */
#define TXY	0xDA /* Transfer X to Y. */
#define STB	0xDC /* STB Absolute. */
#define STB_Z	0xDD /* STore B register. */
#define TXS	0xE0 /* Transfer X to Stack pointer. */
#define LDY	0xE1 /* LoaD Y register. */
#define LDY_AB	0xE4 /* LDY Absolute. */
#define DEC	0xE5 /* DECrement accumulator. */
#define LDY_Z	0xE6 /* LDY Zero Matrix. */
#define BRK	0xE8 /* BReaK. */
#define LDY_ZX	0xE9 /* LDY Zero Matrix, indexed with X. */
#define NOP	0xEA /* No OPeration. */
#define STY	0xEC /* STY Absolute. */
#define STY_Z	0xED /* STore Y register. */
#define DEB	0xEE /* Decrement B register. */
#define ASR	0xF1 /* Arithmetic Shift Right. */
#define ARB	0xF2 /* Arithmetic shift Right accumulator by B. */
#define ASR_AB	0xF4 /* ASR Absolute. */
#define INC	0xF5 /* INCrement accumulator. */
#define ASR_Z	0xF6 /* ASR Zero Matrix. */
#define STY_ZX	0xF9 /* STY Zero Matrix, indexed with X. */
#define STX	0xFC /* STX Absolute. */
#define STX_Z	0xFD /* STore X register. */
#define INB	0xFE /* Increment B register. */

#define OPNUM 90

#define C ((uint64_t)1 << 0)
#define Z ((uint64_t)1 << 1)
#define I ((uint64_t)1 << 2)
#define V ((uint64_t)1 << 6)
#define N ((uint64_t)1 << 7)

uint8_t *addr; /* Address Space. */

struct sux {
	uint64_t ps; /* The processor status register. */
	uint64_t a[8], b[8], y[8], x[8]; /* Registers A, B, X, and Y. */
	uint64_t pc[8]; /* Program counter. */
	uint16_t sp[8]; /* Stack pointer. */
	uint16_t stk_st[8]; /* Starting address of each threads stack. */
	uint8_t crt; /* Current running threads. */
};

enum {IMM, ZM, ZMX, ZMY, IND, INDX, INDY, ABS, IMPL};

static const uint8_t optype[0x100] = {
	[0x00] = IMPL,
	[0x01] = IMM,
	[0x02] = IMPL,
	[0x04] = ABS,
	[0x05] = IND,
	[0x06] = ZM,
	[0x08] = IMM,
	[0x09] = IMM,
	[0x0A] = IMM,
	[0x0C] = ABS,
	[0x0D] = ZM,
	[0x0E] = ZM,
	[0x10] = ABS,
	[0x11] = IMM,
	[0x12] = IMPL,
	[0x14] = ABS,
	[0x15] = IND,
	[0x16] = ZM,
	[0x18] = IMM,
	[0x19] = IMM,
	[0x1A] = IMM,
	[0x1C] = ABS,
	[0x1D] = ZM,
	[0x1E] = ZM,
	[0x20] = ABS,
	[0x21] = IMM,
	[0x22] = IMPL,
	[0x24] = ABS,
	[0x25] = IND,
	[0x26] = ZM,
	[0x28] = IMM,
	[0x29] = IMM,
	[0x2A] = IMM,
	[0x2C] = ABS,
	[0x2D] = ZM,
	[0x2E] = ZM,
	[0x30] = ABS,
	[0x31] = IMM,
	[0x32] = IMPL,
	[0x34] = ABS,
	[0x35] = IND,
	[0x36] = ZM,
	[0x38] = IMM,
	[0x39] = ZMY,
	[0x3A] = IMM,
	[0x3C] = ABS,
	[0x3D] = ZM,
	[0x3E] = ZM,
	[0x40] = ABS,
	[0x41] = IMM,
	[0x42] = IMPL,
	[0x44] = ABS,
	[0x45] = IND,
	[0x46] = ZM,
	[0x48] = IMM,
	[0x49] = ZMY,
	[0x4A] = IMM,
	[0x4C] = ABS,
	[0x4D] = ZM,
	[0x4E] = ZM,
	[0x50] = ABS,
	[0x51] = IMM,
	[0x52] = IMPL,
	[0x54] = ABS,
	[0x55] = IND,
	[0x56] = ZM,
	[0x58] = IMPL,
	[0x59] = ZMY,
	[0x5A] = IMM,
	[0x5C] = INDY,
	[0x5D] = INDX,
	[0x5E] = ZM,
	[0x60] = ABS,
	[0x61] = IMM,
	[0x62] = IMPL,
	[0x64] = ABS,
	[0x65] = IND,
	[0x66] = ZM,
	[0x68] = IMM,
	[0x69] = ZMY,
	[0x6A] = IMPL,
	[0x6C] = INDY,
	[0x6D] = INDX,
	[0x6E] = ZM,
	[0x70] = ABS,
	[0x71] = IMM,
	[0x72] = IMPL,
	[0x74] = ABS,
	[0x75] = IND,
	[0x76] = ZM,
	[0x78] = IMPL,
	[0x79] = ZMX,
	[0x7A] = IMPL,
	[0x7C] = INDY,
	[0x7D] = INDX,
	[0x7E] = ZM,
	[0x80] = ABS,
	[0x81] = IMM,
	[0x82] = IMPL,
	[0x84] = ABS,
	[0x85] = IND,
	[0x86] = ZM,
	[0x88] = IMPL,
	[0x89] = ZMX,
	[0x8A] = IMPL,
	[0x8C] = INDY,
	[0x8D] = INDX,
	[0x8E] = ZM,
	[0x90] = ABS,
	[0x91] = IMM,
	[0x92] = IMPL,
	[0x94] = ABS,
	[0x95] = IND,
	[0x96] = ZM,
	[0x98] = IMPL,
	[0x99] = ZMX,
	[0x9A] = IMPL,
	[0x9C] = INDY,
	[0x9D] = INDX,
	[0x9E] = ZM,
	[0xA0] = ABS,
	[0xA1] = IMM,
	[0xA2] = IMPL,
	[0xA4] = ABS,
	[0xA5] = IND,
	[0xA6] = ZM,
	[0xA8] = IMPL,
	[0xA9] = ZMX,
	[0xAA] = IMPL,
	[0xAC] = INDY,
	[0xAD] = INDX,
	[0xAE] = IMPL,
	[0xB0] = IMPL,
	[0xB1] = IMM,
	[0xB2] = IMPL,
	[0xB4] = ABS,
	[0xB5] = IND,
	[0xB6] = ZM,
	[0xB8] = IMPL,
	[0xB9] = IMM,
	[0xBA] = IMPL,
	[0xBC] = ABS,
	[0xBD] = ZM,
	[0xBE] = IND,
	[0xC0] = IMPL,
	[0xC1] = IMM,
	[0xC4] = ABS,
	[0xC5] = IMPL,
	[0xC6] = ZM,
	[0xC8] = IMPL,
	[0xC9] = ZMY,
	[0xCA] = IMPL,
	[0xCC] = ABS,
	[0xCD] = ZM,
	[0xCE] = IND,
	[0xD0] = IMPL,
	[0xD1] = IMM,
	[0xD4] = ABS,
	[0xD5] = IMPL,
	[0xD6] = ZM,
	[0xD8] = IMPL,
	[0xD9] = ZMY,
	[0xDA] = IMPL,
	[0xDC] = ABS,
	[0xDD] = ZM,
	[0xE0] = IMM,
	[0xE1] = IMM,
	[0xE4] = ABS,
	[0xE5] = IMPL,
	[0xE6] = ZM,
	[0xE8] = IMPL,
	[0xE9] = ZMX,
	[0xEA] = IMPL,
	[0xEC] = ABS,
	[0xED] = ZM,
	[0xEE] = IMPL,
	[0xF1] = IMM,
	[0xF2] = IMPL,
	[0xF4] = ABS,
	[0xF5] = IMPL,
	[0xF6] = ZM,
	[0xF9] = ZMX,
	[0xFC] = ABS,
	[0xFD] = ZM,
	[0xFE] = IMPL
};

#if debug
static const char *opname[0x100] = {
	[0x00] = "CPS",
	[0x01] = "ADC #",
	[0x02] = "AAB",
	[0x04] = "ADC a",
	[0x05] = "LDA ind",
	[0x06] = "ADC zm",
	[0x08] = "PHP #",
	[0x09] = "CPB #",
	[0x0A] = "PHB #",
	[0x0C] = "DEC a",
	[0x0D] = "DEC zm",
	[0x0E] = "JMP zm",
	[0x10] = "JMP a",
	[0x11] = "SBC #",
	[0x12] = "SAB",
	[0x14] = "SBC a",
	[0x15] = "STA ind",
	[0x16] = "SBC zm",
	[0x18] = "ENT #",
	[0x19] = "CPY #",
	[0x1A] = "PLB #",
	[0x1C] = "INC a",
	[0x1D] = "INC zm",
	[0x1E] = "JSR zm",
	[0x20] = "JSL a",
	[0x21] = "AND #",
	[0x22] = "ABA",
	[0x24] = "AND a",
	[0x25] = "CMP ind",
	[0x26] = "AND zm",
	[0x28] = "PLP #",
	[0x29] = "CPX #",
	[0x2A] = "PHY #",
	[0x2C] = "CPB a",
	[0x2D] = "CPB zm",
	[0x2E] = "BPO zm",
	[0x30] = "BPO a",
	[0x31] = "ORA #",
	[0x32] = "OAB",
	[0x34] = "ORA a",
	[0x35] = "LDB ind",
	[0x36] = "ORA zm",
	[0x38] = "STT #",
	[0x39] = "LDA zmy",
	[0x3A] = "PLY #",
	[0x3C] = "CPX a",
	[0x3D] = "CPY zm",
	[0x3E] = "BNG zm",
	[0x40] = "BNG a",
	[0x41] = "XOR #",
	[0x42] = "XAB",
	[0x44] = "XOR a",
	[0x45] = "STB ind",
	[0x46] = "XOR zm",
	[0x48] = "PHA #",
	[0x49] = "STA zmy",
	[0x4A] = "PHX #",
	[0x4C] = "CPY a",
	[0x4D] = "CPX zm",
	[0x4E] = "BCS zm",
	[0x50] = "BCS a",
	[0x51] = "LSL #",
	[0x52] = "LLB",
	[0x54] = "LSL a",
	[0x55] = "CPB ind",
	[0x56] = "LSL zm",
	[0x58] = "CLC",
	[0x59] = "LDB zmy",
	[0x5A] = "PLX #",
	[0x5C] = "LDA iny",
	[0x5D] = "LDA inx",
	[0x5E] = "BCC zm",
	[0x60] = "BCC a",
	[0x61] = "LSR #",
	[0x62] = "LRB",
	[0x64] = "LSR a",
	[0x65] = "LDY ind",
	[0x66] = "LSR zm",
	[0x68] = "PLA #",
	[0x69] = "STB zmy",
	[0x6A] = "TAB",
	[0x6C] = "STA iny",
	[0x6D] = "STA inx",
	[0x6E] = "BEQ zm",
	[0x70] = "BEQ a",
	[0x71] = "ROL #",
	[0x72] = "RLB",
	[0x74] = "ROL a",
	[0x75] = "STY ind",
	[0x76] = "ROL zm",
	[0x78] = "SEC",
	[0x79] = "LDA zmx",
	[0x7A] = "TBA",
	[0x7C] = "CMP iny",
	[0x7D] = "CMP inx",
	[0x7E] = "BNE zm",
	[0x80] = "BNE a",
	[0x81] = "ROR #",
	[0x82] = "RRB",
	[0x84] = "ROR a",
	[0x85] = "CPY ind",
	[0x86] = "ROR zm",
	[0x88] = "DEY",
	[0x89] = "STA zmx",
	[0x8A] = "TAY",
	[0x8C] = "LDB iny",
	[0x8D] = "LDB inx",
	[0x8E] = "BVS zm",
	[0x90] = "BVS a",
	[0x91] = "MUL #",
	[0x92] = "MAB",
	[0x94] = "MUL a",
	[0x95] = "LDX ind",
	[0x96] = "MUL zm",
	[0x98] = "CLI",
	[0x99] = "LDB zmx",
	[0x9A] = "TYA",
	[0x9C] = "STB iny",
	[0x9D] = "STB inx",
	[0x9E] = "BVC zm",
	[0xA0] = "BVC a",
	[0xA1] = "DIV #",
	[0xA2] = "DAB",
	[0xA4] = "DIV a",
	[0xA5] = "STX ind",
	[0xA6] = "DIV zm",
	[0xA8] = "INY",
	[0xA9] = "STB zmx",
	[0xAA] = "TAX",
	[0xAC] = "CPB iny",
	[0xAD] = "CPB inx",
	[0xAE] = "RTS",
	[0xB0] = "RTL",
	[0xB1] = "CMP #",
	[0xB2] = "CAB",
	[0xB4] = "CMP a",
	[0xB5] = "CPX ind",
	[0xB6] = "CMP zm",
	[0xB8] = "SEI",
	[0xB9] = "LDX #",
	[0xBA] = "TXA",
	[0xBC] = "LDX a",
	[0xBD] = "LDX zm",
	[0xBE] = "JSR ind",
	[0xC0] = "RTI",
	[0xC1] = "LDA #",
	[0xC4] = "LDA a",
	[0xC5] = "DEX",
	[0xC6] = "LDA zm",
	[0xC8] = "CLV",
	[0xC9] = "LDX zmy",
	[0xCA] = "TYX",
	[0xCC] = "STA a",
	[0xCD] = "STA zm",
	[0xCE] = "JMP ind",
	[0xD0] = "TSX",
	[0xD1] = "LDB #",
	[0xD4] = "LDB a",
	[0xD5] = "INX",
	[0xD6] = "LDB zm",
	[0xD8] = "WAI",
	[0xD9] = "STX zmy",
	[0xDA] = "TXY",
	[0xDC] = "STB a",
	[0xDD] = "STB zm",
	[0xE0] = "TXS #",
	[0xE1] = "LDY #",
	[0xE4] = "LDY a",
	[0xE5] = "DEC A",
	[0xE6] = "LDY zm",
	[0xE8] = "BRK",
	[0xE9] = "LDY zmx",
	[0xEA] = "NOP",
	[0xEC] = "STY a",
	[0xED] = "STY zm",
	[0xEE] = "DEB",
	[0xF1] = "ASR #",
	[0xF2] = "ARB",
	[0xF4] = "ASR a",
	[0xF5] = "INC A",
	[0xF6] = "ASR zm",
	[0xF9] = "STY zmx",
	[0xFC] = "STX a",
	[0xFD] = "STX zm",
	[0xFE] = "INB"
};
#endif

extern int asmmon();