summaryrefslogtreecommitdiff
path: root/sux.c
blob: dcdd79b9d1ce03811f44e297591089117e6033f6 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
#include "sux.h"
#include <assert.h>
#include <ctype.h>
#include <string.h>

#if getclk
uint64_t clk[THREADS];	/* Per Thread Clock cycles. */
uint64_t tclk;		/* Total Clock cycles. */
#endif

const uint16_t tv = 0xFF50; /* Starting address of the Thread Vectors. */

#if !IO
uint64_t inst[THREADS];
#endif

#if bench
uint64_t inss;
#endif

#if debug
uint8_t subdbg;
#endif

pthread_mutex_t mutex = PTHREAD_MUTEX_INITIALIZER;
pthread_mutex_t main_mutex = PTHREAD_MUTEX_INITIALIZER;
pthread_cond_t cond = PTHREAD_COND_INITIALIZER;
pthread_cond_t main_cond = PTHREAD_COND_INITIALIZER;

uint8_t threads_done = 0;
uint8_t step = 0;

uint8_t *addr;

uint8_t kbd_rdy;

WINDOW *scr;

struct suxthr {
	struct sux sx;
	uint8_t th;
};

#if bench
double ipc;
struct timeval str[THREADS], en[THREADS];
#endif

void *run(void *args) {
	struct suxthr *thr = (void *)args;
	struct sux *cpu = &thr->sx;
	uint8_t thread = thr->th;
	uint8_t prefix = 0;
	uint8_t opcode = 0;
	uint8_t esc = 0;
	union reg address;
	union reg value;
	#if getclk
	uint64_t iclk = 0;
	#endif
	#if !IO
	uint64_t ins = 0;
	#endif
#if !bench
	uint8_t lines = (6*thread)+2;
#endif
#if debug && !bench
	if (!subdbg) {
		addr[STEP_ADDR] = 1;
		step = 1;
	}
	#if keypoll
	pthread_mutex_lock(&mutex);
	#endif
	werase(scr);
	#if keypoll
	pthread_mutex_unlock(&mutex);
	#endif
#endif
	uint64_t tmpaddr = 0;
#if bench
	gettimeofday(&str[thread], 0);
#endif
	for (;;) {
		address.u64 = 0;
		value.u64 = 0;
		prefix = addr[cpu->pc[thread]];
		if ((prefix & 0x03) != 0x03) {
			prefix = 0;
		}
		cpu->pc[thread] += ((prefix & 0x03) == 0x03);
		opcode = addr[cpu->pc[thread]];
		#if debug && !bench
		if (lines > 24*(thread+1)) {
			lines = (24*thread)+2;
		}
		#if keypoll
		pthread_mutex_lock(&mutex);
		#endif
		for (uint8_t i = (24*thread)+2; i <= 24*(thread+1); i++) {
			wmove(scr, i, 0);
			waddch(scr, (i == lines) ? '>' : ' ');
		}
		wmove(scr, lines, 1);
		wclrtoeol(scr);
		wprintw(scr,
			"pc: $%04"PRIX64
			", a: $%016"PRIX64
			", b: $%016"PRIX64
			", x: $%016"PRIX64
			", y: $%016"PRIX64
			, cpu->pc[thread]
			, cpu->a[thread]
			, cpu->b[thread]
			, cpu->x[thread]
			, cpu->y[thread]);
		wprintw(scr,
			", sp: $%04X"
			", ps: $%02X"
			", inst: "
			, cpu->sp[thread]
			, cpu->ps.u8[thread]);
		#if keypoll
		pthread_mutex_unlock(&mutex);
		#endif
		#endif
		address.u64 = cpu->pc[thread];
		++cpu->pc[thread];
		#if getclk
		++iclk;
		#endif
		if (optype[opcode] != IMPL) {
			address.u64 = get_addr(cpu, &tmpaddr, opcode, prefix, thread);
			/* Unroll Loop by implementing Duff's Device. */
			value.u8[0] = addr[address.u64];
			switch (1 << (prefix >> 4)) {
				case 8:
					value.u8[7] = addr[address.u64+7];
					value.u8[6] = addr[address.u64+6];
					value.u8[5] = addr[address.u64+5];
					value.u8[4] = addr[address.u64+4];
				case 4:
					value.u8[3] = addr[address.u64+3];
					value.u8[2] = addr[address.u64+2];
				case 2:
					value.u8[1] = addr[address.u64+1];
			}
			#if getclk
			++iclk;
			#endif
		}
	#if debug && !bench
		#if keypoll
		pthread_mutex_lock(&mutex);
		#endif
		uint64_t operands[3];
		operands[0] = value.u64;
		operands[1] = address.u64;
		operands[2] = tmpaddr;
		disasm(cpu, operands, lines, opcode, prefix, thread);
		lines+=1;
		#if keypoll
		pthread_mutex_unlock(&mutex);
		#endif
	#endif
		switch(opcode) {
			case CPS: /* Clear Processor Status. */
				cpu->ps.u64 = 0;
				break;
			case AAB: /* Add Accumulator with carry by B register. */
				value.u64 = cpu->b[thread]; /* Falls Through. */
			case ADC:  /* ADC Immediate. */
			case ADC_AB: /* ADC Absolute. */
			case ADC_Z: /* ADC Zero Matrix. */
				adc(cpu, value.u64, thread);
				break;
			case PHB: /* PusH B register to stack. */
			case PHP: /* PusH Processor status to stack. */
			case PHA: /* PusH Accumulator to stack. */
			case PHY: /* PusH Y register to stack. */
			case PHX: /* PusH X register to stack. */
				push(cpu, value.u64, opcode, thread);
				break;
			case TAY: /* Transfer Accumulator to Y. */
			case TAX: /* Transfer Accumulator to Y. */
			case TYX: /* Transfer Y to X. */
			case TYA: /* Transfer Y to Accumulator. */
			case TXA: /* Transfer X to Accumulator. */
			case TXY: /* Transfer X to Y. */
			case TAB: /* Transfer Accumulator to B. */
			case TSX: /* Transfer Stack pointer to X. */
			case TBA: /* Transfer B to Accumulator. */
			case TXS: /* Transfer X to Stack pointer. */
				transfer(cpu, value.u64, opcode, prefix, thread);
				break;
			case JMP: /* JMP Absolute. */
			case JMP_Z: /* JMP Zero Matrix. */
			case JMP_IN: /* JMP Indirect. */
				cpu->pc[thread] = address.u64;
				break;
			case SAB: /* Subtract Accumulator with carry by B register. */
				value.u64 = cpu->b[thread]; /* Falls Through. */
			case SBC: /* SBC Immediate. */
			case SBC_AB: /* SBC Absolute. */
			case SBC_Z: /* SBC Zero Matrix. */
				sbc(cpu, value.u64, thread);
				break;
			case PLB: /* PuLl B register from stack. */
			case PLP: /* PuLl Processor status from stack. */
			case PLA: /* PuLl Accumulator from stack. */
			case PLY: /* PuLl Y register from stack. */
			case PLX: /* PuLl X register from stack. */
				pull(cpu, value.u64, opcode, thread);
				break;
			case ABA: /* bitwise And with Accumulator, and B register. */
				value.u64 = cpu->b[thread]; /* Falls Through. */
			case AND: /* AND Immediate. */
			case AND_AB: /* AND Absolute. */
			case AND_Z: /* AND Zero Matrix. */
				and(cpu, value.u64, thread);
				break;
			case STT: /* STart Thread. */
				/*cpu->crt |= value;
				for (uint8_t i = 0; i < 7; i++) {
					if ((value >> i) & 1) {
						address = (uint64_t)addr[tv+(i<<3)]
								| (uint64_t)addr[tv+1+(i<<3)] << 8
								| (uint64_t)addr[tv+2+(i<<3)] << 16
								| (uint64_t)addr[tv+3+(i<<3)] << 24
								| (uint64_t)addr[tv+4+(i<<3)] << 32
								| (uint64_t)addr[tv+5+(i<<3)] << 40
								| (uint64_t)addr[tv+6+(i<<3)] << 48
								| (uint64_t)addr[tv+7+(i<<3)] << 56;
						cpu->pc[i+1] = address;
					}
				}*/
				break;
			case BPO: /* BPO Absolute. */
			case BPO_Z: /* BPO Zero Matrix. */
				if (!getflag(N)) {
					cpu->pc[thread] = address.u64;
				}
				break;
			case OAB: /* bitwise Or with Accumulator, and B register. */
				value.u64 = cpu->b[thread]; /* Falls Through. */
			case ORA: /* ORA Immediate. */
			case ORA_AB: /* ORA Absolute. */
			case ORA_Z: /* ORA Zero Matrix. */
				or(cpu, value.u64, thread);
				break;
			case SEI: /* SEt Interrupt. */
				setflag(1, I);
				break;
			case BNG: /* BNG Absolute. */
			case BNG_Z: /* BNG Zero Matrix. */
				if (getflag(N)) {
					cpu->pc[thread] = address.u64;
				}
				break;
			case XAB: /* bitwise Xor with Accumulator, and B register. */
				value.u64 = cpu->b[thread]; /* Falls Through. */
			case XOR: /* XOR Immediate. */
			case XOR_AB: /* XOR Absolute. */
			case XOR_Z: /* XOR Zero Matrix. */
				xor(cpu, value.u64, thread);
				break;
			case CLI: /* CLear Interrupt. */
				setflag(0, I);
				break;
			case BCS: /* BCS Absolute. */
			case BCS_Z: /* BCS Zero Matrix. */
				if (getflag(C)) {
					cpu->pc[thread] = address.u64;
				}
				break;
			case LLB: /* Logical shift Left accumulator by B. */
				value.u64 = cpu->b[thread]; /* Falls Through. */
			case LSL: /* LSL Immediate. */
			case LSL_AB: /* LSL Absolute. */
			case LSL_Z: /* LSL Zero Matrix. */
				lsl(cpu, value.u64, thread);
				break;
			case SEC: /* SEt Carry flag.*/
				setflag(1, C);
				break;
			case STA: /* STA Absolute. */
			case STY: /* STY Absolute. */
			case STX: /* STX Absolute. */
			case STB: /* STB Absolute. */
			case STA_Z: /* STA Zero Matrix. */
			case STY_Z: /* STY Zero Matrix. */
			case STX_Z: /* STX Zero Matrix. */
			case STB_Z: /* STB Zero Matrix. */
			case STA_ZX: /* STA Zero Matrix, Indexed with X. */
			case STY_ZX: /* STY Zero Matrix, Indexed with X. */
			case STX_ZY: /* STX Zero Matrix, Indexed with Y. */
			case STB_ZX: /* STB Zero Matrix, Indexed with X. */
			case STA_ZY: /* STA Zero Matrix, Indexed with Y. */
			case STB_ZY: /* STB Zero Matrix, Indexed with Y. */
			case STY_IN: /* STY Indirect. */
			case STX_IN: /* STX Indirect. */
			case STA_IN: /* STA Indirect. */
			case STB_IN: /* STB Indirect. */
			case STA_IX: /* STA Indexed Indirect. */
			case STB_IX: /* STB Indexed Indirect. */
			case STA_IY: /* STA Indirect Indexed. */
			case STB_IY: /* STB Indirect Indexed. */
				store(cpu, address.u64, &esc, opcode, prefix, thread);
				step = addr[STEP_ADDR] || cpu->pc[thread] == CTRL_ADDR;
				break;
			case BCC: /* BCC Absolute. */
			case BCC_Z: /* BCC Zero Matrix. */
				if (!getflag(C)) {
					cpu->pc[thread] = address.u64;
				}
				break;
			case LRB: /* Logical shift Right accumulator by B. */
				value.u64 = cpu->b[thread]; /* Falls Through. */
			case LSR: /* LSR Immediate. */
			case LSR_AB: /* LSR Absolute. */
			case LSR_Z: /* LSR Zero Matrix. */
				lsr(cpu, value.u64, thread);
				break;
			case ARB: /* Arithmetic shift Right accumulator by B. */
				value.u64 = cpu->b[thread]; /* Falls Through. */
			case ASR: /* ASR Immediate. */
			case ASR_AB: /* ASR Absolute. */
			case ASR_Z: /* ASR Zero Matrix. */
				asr(cpu, value.u64, thread);
				break;
			case CLC: /* CLear Carry flag. */
				setflag(0, C);
				break;
			case LDB: /* LDB Immediate. */
			case LDA: /* LDA Immediate. */
			case LDY: /* LDY Immediate. */
			case LDX: /* LDX Immediate. */
			case LDB_AB: /* LDB Absolute. */
			case LDA_AB: /* LDA Absolute. */
			case LDY_AB: /* LDY Absolute. */
			case LDX_AB: /* LDX Absolute. */
			case LDB_Z: /* LDB Zero Matrix. */
			case LDA_Z: /* LDA Zero Matrix. */
			case LDY_Z: /* LDY Zero Matrix. */
			case LDX_Z: /* LDX Zero Matrix. */
			case LDB_ZX: /* LDB Zero Matrix, Indexed with X. */
			case LDA_ZX: /* LDA Zero Matrix, Indexed with X. */
			case LDY_ZX: /* LDY Zero Matrix, Indexed with X. */
			case LDX_ZY: /* LDX Zero Matrix, Indexed with Y. */
			case LDB_ZY: /* LDB Zero Matrix, Indexed with Y. */
			case LDA_ZY: /* LDA Zero Matrix, Indexed with Y. */
			case LDB_IN: /* LDY Indirect. */
			case LDA_IN: /* LDX Indirect. */
			case LDY_IN: /* LDB Indirect. */
			case LDX_IN: /* LDA Indirect. */
			case LDB_IX: /* LDB Indexed Indirect. */
			case LDA_IX: /* LDA Indexed Indirect. */
			case LDB_IY: /* LDB Indirect Indexed. */
			case LDA_IY: /* LDA Indirect Indexed. */
				load(cpu, address.u64, &esc, opcode, prefix, thread);
				break;
			case BEQ: /* BEQ Absolute. */
			case BEQ_Z: /* BEQ Zero Matrix. */
				if (getflag(Z)) {
					cpu->pc[thread] = address.u64;
				}
				break;
			case RLB: /* Rotate Left accumulator by B. */
				value.u64 = cpu->b[thread]; /* Falls Through. */
			case ROL: /* ROL Immediate. */
			case ROL_AB: /* ROL Absolute. */
			case ROL_Z: /* ROL Zero Matrix. */
				rol(cpu, value.u64, thread);
				break;
			case BNE: /* BNE Absolute. */
			case BNE_Z: /* BNE Zero Matrix. */
				if (!getflag(Z)) {
					cpu->pc[thread] = address.u64;
				}
				break;
			case RRB: /* Rotate Right accumulator by B. */
				value.u64 = cpu->b[thread]; /* Falls Through. */
			case ROR: /* ROR Immediate. */
			case ROR_AB: /* ROR Absolute. */
			case ROR_Z: /* ROR Zero Matrix. */
				ror(cpu, value.u64, thread);
				break;
			case BVS: /* BVS Absolute. */
			case BVS_Z: /* BVS Zero Matrix. */
				if (getflag(V)) {
					cpu->pc[thread] = address.u64;
				}
				break;
			case MAB: /* Multiply Accumulator by B. */
				value.u64 = cpu->b[thread]; /* Falls Through. */
			case MUL: /* MUL Immediate. */
			case MUL_AB: /* MUL Absolute. */
			case MUL_Z: /* MUL Zero Matrix. */
				mul(cpu, value.u64, thread);
				break;
			case BVC: /* BVC Absolute. */
			case BVC_Z: /* BVC Zero Matrix. */
				if (!getflag(V)) {
					cpu->pc[thread] = address.u64;
				}
				break;
			case DIV: /* DIV Immediate. */
			case DAB: /* Divide Accumulator by B. */
			case DIV_AB: /* DIV Absolute. */
			case DIV_Z: /* DIV Zero Matrix. */
				divd(cpu, value.u64, opcode, thread);
				break;
			case CLV: /* CLear oVerflow flag. */
				setflag(0, V);
				break;
			case CAB: /* Compare Accumulator, and B. */
				value.u64 = cpu->b[thread]; /* Falls Through. */
			case CPB: /* CPB Immediate. */
			case CMP: /* CMP Immediate. */
			case CPY: /* CPY Immediate. */
			case CPX: /* CPX Immediate. */
			case CPY_AB: /* CPY Absolute. */
			case CPX_AB: /* CPX Absolute. */
			case CMP_AB: /* CMP Absolute. */
			case CPB_AB: /* CPB Absolute. */
			case CPY_Z: /* CPY Zero Matrix. */
			case CPX_Z: /* CPX Zero Matrix. */
			case CMP_Z: /* CMP Zero Matrix. */
			case CPB_Z: /* CPB Zero Matrix. */
			case CPY_IN: /* CMP Indirect. */
			case CPX_IN: /* CPY Indirect. */
			case CMP_IN: /* CPX Indirect. */
			case CPB_IN: /* CPB Indirect. */
			case CMP_IX: /* CMP Indexed Indirect. */
			case CPB_IX: /* CPB Indexed Indirect. */
			case CMP_IY: /* CMP Indirect Indexed. */
			case CPB_IY: /* CPB Indirect Indexed. */
				cmp(cpu, value.u64, opcode, thread);
				break;
			case ENT: /* ENd Thread. */
			/*	cpu->crt &= ~value;
				for (uint8_t i = 0; i < 7; i++)
					if ((value >> i) & 1)
						cpu->pc[i+1] = cpu->pc[0]+(i+1);*/
				break;
			case INC: /* INC Accumulator. */
			case INB:
			case INY:
			case INX:
				incr(cpu, opcode, thread);
				break;
			case DEC: /* DEC Accumulator. */
			case DEB:
			case DEY:
			case DEX:
				decr(cpu, opcode, thread);
				break;
			case JSR_IN: /* JSR Indirect. */
			case JSR: /* Jump to SubRoutine. */
			case JSR_Z: /* JSR Zero Matrix. */
				value.u64 = cpu->pc[thread];
				addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]-0] = value.u8[7];
				addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]-1] = value.u8[6];
				addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]-2] = value.u8[5];
				addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]-3] = value.u8[4];
				addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]-4] = value.u8[3];
				addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]-5] = value.u8[2];
				addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]-6] = value.u8[1];
				addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]-7] = value.u8[0];
				cpu->sp[thread] -= 8;
				cpu->pc[thread] = address.u64;
				break;
			case INC_AB: /* INC Absolute. */
			case INC_Z: /* INC Zero Matrix. */
				incm(cpu, address.u64, thread);
				step = addr[STEP_ADDR] || cpu->pc[thread] == CTRL_ADDR;
				break;
			case NOP: /* No OPeration. */
				break;
			case RTI: /* ReTurn from Interrupt routine. */
				cpu->sp[thread]   += 1;
				cpu->ps.u8[thread] = addr[(cpu->stk_st[thread] << 16)+(cpu->sp[thread])]; /* Falls through. */
			case RTS: /* ReTurn from Subroutine. */
				cpu->sp[thread] += 8;
				value.u8[0] = addr[(cpu->stk_st[thread] << 16)+(cpu->sp[thread]-7)];
				value.u8[1] = addr[(cpu->stk_st[thread] << 16)+(cpu->sp[thread]-6)];
				value.u8[2] = addr[(cpu->stk_st[thread] << 16)+(cpu->sp[thread]-5)];
				value.u8[3] = addr[(cpu->stk_st[thread] << 16)+(cpu->sp[thread]-4)];
				value.u8[4] = addr[(cpu->stk_st[thread] << 16)+(cpu->sp[thread]-3)];
				value.u8[5] = addr[(cpu->stk_st[thread] << 16)+(cpu->sp[thread]-2)];
				value.u8[6] = addr[(cpu->stk_st[thread] << 16)+(cpu->sp[thread]-1)];
				value.u8[7] = addr[(cpu->stk_st[thread] << 16)+(cpu->sp[thread]  )];
				cpu->pc[thread] = value.u64;
				break;
			case DEC_AB: /* DEC Absolute. */
			case DEC_Z: /* DEC Zero Matrix. */
				decm(cpu, address.u64, thread);
				step = addr[STEP_ADDR] || cpu->pc[thread] == CTRL_ADDR;
				break;
			case BRK: /* BReaK. */
			case WAI: /* WAit for Interrupt. */
				if (opcode == WAI) {
					pthread_mutex_lock(&main_mutex);
					pthread_cond_signal(&main_cond);
					pthread_mutex_unlock(&main_mutex);
					pthread_mutex_lock(&mutex);
					pthread_cond_wait(&cond, &mutex);
					pthread_mutex_unlock(&mutex);
				}
				value.u64 = cpu->pc[thread];
				addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]-0] = value.u8[7];
				addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]-1] = value.u8[6];
				addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]-2] = value.u8[5];
				addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]-3] = value.u8[4];
				addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]-4] = value.u8[3];
				addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]-5] = value.u8[2];
				addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]-6] = value.u8[1];
				addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]-7] = value.u8[0];
				addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]-8] = cpu->ps.u8[thread];
				cpu->sp[thread] -= 9;
				setflag(1, I);
				if (opcode == BRK) {
					value.u8[0] = addr[0xFFE0];
					value.u8[1] = addr[0xFFE1];
					value.u8[2] = addr[0xFFE2];
					value.u8[3] = addr[0xFFE3];
					value.u8[4] = addr[0xFFE4];
					value.u8[5] = addr[0xFFE5];
					value.u8[6] = addr[0xFFE6];
					value.u8[7] = addr[0xFFE7];
				} else {
					value.u8[0] = addr[0xFFA0];
					value.u8[1] = addr[0xFFA1];
					value.u8[2] = addr[0xFFA2];
					value.u8[3] = addr[0xFFA3];
					value.u8[4] = addr[0xFFA4];
					value.u8[5] = addr[0xFFA5];
					value.u8[6] = addr[0xFFA6];
					value.u8[7] = addr[0xFFA7];
					kbd_rdy &= (uint8_t)~(1 << thread);
				}
				cpu->pc[thread] = value.u64;
			default:
				break;
		}
		#if !IO
		ins++;
		#endif
		#if !bench
		if (step) {
			pthread_mutex_lock(&main_mutex);
			pthread_cond_signal(&main_cond);
			pthread_mutex_unlock(&main_mutex);
			pthread_mutex_lock(&mutex);
			pthread_cond_wait(&cond, &mutex);
			pthread_mutex_unlock(&mutex);
			#if debug
			wrefresh(scr);
			#endif
		}
		#endif
		#if debug && !bench
		#if keypoll
		pthread_mutex_lock(&mutex);
		#endif
		wmove(scr, (6*thread)+1, 0);
		wprintw(scr, "Instructions executed: %"PRIu64, ins);
		#if getclk
		wprintw(scr, ", Clock cycles: %"PRIu64, iclk);
		#endif
		if (!step && !subdbg) {
			wrefresh(scr);
		}
		#if keypoll
		pthread_mutex_unlock(&mutex);
		#endif
		#elif bench
		if (ins >= BENCH_INST) {
			pthread_mutex_lock(&main_mutex);
			threads_done++;
			inst[thread] = ins;
			#if getclk
			clk[thread] = iclk;
			#endif
			pthread_cond_signal(&main_cond);
			pthread_mutex_unlock(&main_mutex);
			gettimeofday(&en[thread], 0);
			break;
		}
		#endif
	}
	return NULL;
}

int main(int argc, char **argv) {
	struct suxthr thr[THREADS];
	char *tmp = malloc(2048);
	addr = malloc(0x04000000);
	#if bench
	inss = 0;
	#endif
	int v = 0;

	if (argc != 2) {
		if (asmmon("stdin") == 2) {
			return 0;
		}
	} else {
		#if debug
		subdbg = !strcmp(argv[1], "programs/subeditor.s");
		#endif
		if (asmmon(argv[1]) == 2) {
			return 0;
		}
	}
	sprintf(tmp, "\033[2J\033[H");
	fwrite(tmp, sizeof(char), strlen(tmp), stdout);
	fflush(stdout);
	if(!scr) {
		scr = initscr();
	}
	nodelay(stdscr, 0);
	crmode();
	noecho();
	nl();
	curs_set(1);
	werase(scr);
	scrollok(scr, 1);
	start_color();
	use_default_colors();
	init_pair(1, COLOR_WHITE, -1);
	attron(COLOR_PAIR(1) | A_BOLD);
	wmove(scr, 0, 0);
	wrefresh(scr);
	pthread_t therads[THREADS];
	int result;
	uint16_t vec = 0xFFC0;
	uint8_t offset;
	for (int i = 0; i < THREADS; i++) {
		thr[i].sx.sp[i] = 0xFFFF;
		thr[i].sx.stk_st[i] = i+1;
		offset = (i) ? ((i-1) << 3) : 0;
		vec = (i) ? 0xFF50 : 0xFFC0;
		thr[i].sx.a[i] = 0;
		thr[i].sx.b[i] = 0;
		thr[i].sx.x[i] = 0;
		thr[i].sx.y[i] = 0;
		thr[i].sx.pc[i] = (uint64_t)addr[vec+0+offset]
				| (uint64_t)addr[vec+1+offset] << 8
				| (uint64_t)addr[vec+2+offset] << 16
				| (uint64_t)addr[vec+3+offset] << 24
				| (uint64_t)addr[vec+4+offset] << 32
				| (uint64_t)addr[vec+5+offset] << 40
				| (uint64_t)addr[vec+6+offset] << 48
				| (uint64_t)addr[vec+7+offset] << 56;

		thr[i].th = i;
		#if !IO
		inst[i] = 0;
		#endif
		result = pthread_create(&therads[i], NULL, run, &thr[i]);
		assert(!result);
	}
	int c = 0;
	uint8_t step_key = 0;
	uint8_t end = 0;
	werase(scr);
	while (threads_done < THREADS && !end) {
		#if !bench
		int x, y;
		if ((step_key && step && !kbd_rdy) || !step || kbd_rdy) {
			if ((c != EOF && c !=-1)) {
				#if !keypoll
				pthread_mutex_lock(&mutex);
				pthread_cond_signal(&cond);
				pthread_mutex_unlock(&mutex);
				#endif
				pthread_mutex_lock(&main_mutex);
				curs_set(0);
				pthread_cond_wait(&main_cond, &main_mutex);
				pthread_mutex_unlock(&main_mutex);
				curs_set(1);
				c = 0;
				step_key = 0;
				addr[CTRL_ADDR] = 0;
				wrefresh(scr);
			}
		}
		#if keypoll
		pthread_mutex_lock(&mutex);
		#endif
		c = wgetch(scr);
		if (c == 19) {
			if (kbd_rdy) {
				c = wgetch(scr);
			}
			step = 1;
		} else if (c == 0x11) {
			end = 1;
			continue;
		}
		if (kbd_rdy) {
			switch (c) {
				case ERR:
					addr[CTRL_ADDR] = 0;
					break;
				default:
					if (kbd_rdy && c < 0x100) {
						addr[RX_ADDR] = (uint8_t)c;
						addr[CTRL_ADDR] = 1;
						#if debug && !bench
						wmove(scr, getmaxy(scr)-1, 0);
						wclrtoeol(scr);
						wprintw(scr, "c: %i", c);
						wmove(scr, y, x);
						#endif
					}
					break;
			}
		} else {
			if (step) {
				step = !(c == 18);
				step_key = (c == 19);
			}
		}
		addr[STEP_ADDR] = step;
		#if keypoll
		pthread_mutex_unlock(&mutex);
		#endif
		#else
		pthread_mutex_lock(&main_mutex);
		pthread_cond_wait(&main_cond, &main_mutex);
		pthread_mutex_unlock(&main_mutex);
		#endif
	}
	endwin();
#if bench
	if (threads_done == THREADS) {
		double tm_sec, tm_usec, tm[THREADS], ttm;
		#if getclk
		double clkspd;
		double mhz;
		#endif
		double ips[THREADS];
		double ipst;
		for (int i = 0; i < THREADS; i++) {
			tm_sec = (en[i].tv_sec - str[i].tv_sec);
			tm_usec = (en[i].tv_usec-str[i].tv_usec);
			tm[i] = (tm_sec*1000000)+(tm_usec);
			ips[i] = inst[i]/tm[i];
			if (i) {
				inss += inst[i];
				ttm += tm[i];
				ipst += ips[i];
				#if getclk
				tclk += clk[i];
				#endif
			} else {
				inss = inst[i];
				ttm = tm[i];
				ipst = ips[i];
				#if getclk
				tclk = clk[i];
				#endif
			}
			#if getclk
			clkspd = (tm[i]/1000000)*1000000/clk[i];
			mhz = 1000000.0/clkspd/1000000;
			#endif
			sprintf(tmp, "Instructions executed for thread %i: %"PRIu64", Instructions per Second for thread %i in MIPS: %f, tm: %f\n", i, inst[i], i, ips[i], tm[i]/1000000);
			fwrite(tmp, sizeof(char), strlen(tmp), stdout);
		}
		sprintf(tmp, "Total Instructions executed: %"PRIu64", Total Instructions per Second in MIPS: %f", inss, ipst);
		fwrite(tmp, sizeof(char), strlen(tmp), stdout);
		#if getclk
		clkspd = (ttm/1000000)*1000000/tclk;
		mhz = 1000000.0/clkspd/1000000;
		sprintf(tmp, ", Clock cycles: %"PRIu64", Clock Speed in MHz: %f", tclk, mhz);
		fwrite(tmp, sizeof(char), strlen(tmp), stdout);
		#endif
		sprintf(tmp, ", tm: %f\n", ttm/1000000);
		fwrite(tmp, sizeof(char), strlen(tmp), stdout);
		fflush(stdout);
		free(tmp);
	}
#endif
	free(addr);
	return 0;
}