sux.h: Fix some bugs in the interrupt bitmasks.

1 files changed, 17 insertions, 16 deletions

diff --git a/sux.h b/sux.h
index 079750c..949ccd1 100644
--- a/sux.h
+++ b/sux.h
@@ -1814,18 +1814,18 @@ static /*inline*/ void inst_##op(struct sux *cpu, uint8_t prefix, uint8_t size,
 	uint64_t dummy2 = 0, *reg2 = &dummy2; \
 	int pre_idx = 0, mem_type = ZM; \
 	/* Decode Address. */ \
-	t(1, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000) { cpu->pc = 0xFFA0; } /* NMI Vector. */ \
-	t(2, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000) { cpu->pc = 0xFFC0; } /* Reset Vector. */ \
-	t(4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000) { cpu->pc = 0xFFE0; } /* IRQ Vector. */ \
-	t(0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000200, 0x00000000, 0x00000000, 0x00000000) { cpu->pc = 0xFFF0; } /* BRK Vector. */ \
-	t(7, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000200, 0x00000000, 0x00000000, 0x00000000) { prefix = 0x0F; } /* Interrupts. */ \
-	t(7, 0x00060000, 0x00060000, 0x00160000, 0x00160000, 0x01160200, 0x01160000, 0x01170000, 0x01170000) { mem_type = ABS; } /* Interrupts, and absolute. */ \
+	t(1, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000) { addr = 0xFFA0; } /* NMI Vector. */ \
+	t(2, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000) { addr = 0xFFC0; } /* Reset Vector. */ \
+	t(4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000) { addr = 0xFFE0; } /* IRQ Vector. */ \
+	t(0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000200, 0x00000000, 0x00000000, 0x00000000) { addr = 0xFFF0; } /* BRK Vector. */ \
+	t(7, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000200, 0x00000000, 0x00000000, 0x00000000) { rs = 7; } /* Interrupts. */ \
+	t(0, 0x00060000, 0x00060000, 0x00160000, 0x00160000, 0x01160000, 0x01160000, 0x01170000, 0x01170000) { mem_type = ABS; } /* Absolute. */ \
 	t(0, 0x01000100, 0x01000100, 0x04000400, 0x00000000, 0x00000000, 0x40004000, 0x40004000, 0x00000000) { idx = cpu->x; } /* Register index. */ \
 	t(0, 0x06400200, 0x06400400, 0x00000000, 0x00000000, 0x00000000, 0x10000000, 0x10000000, 0x00000000) { idx = cpu->y; } \
-	t(7, 0x00460160, 0x00460160, 0x00160160, 0x00160160, 0x01161360, 0x11165161, 0x11175161, 0x01171160) { addr = read_addr(cpu, prefix, inc_clk, mem_type, inc_pc) + idx; } /* Read address from memory. */ \
+	t(0, 0x00460160, 0x00460160, 0x00160160, 0x00160160, 0x01161160, 0x11165161, 0x11175161, 0x01171160) { addr = read_addr(cpu, prefix, inc_clk, mem_type, inc_pc) + idx; } /* Read address from memory. */ \
 	t(0, 0x01000000, 0x01000000, 0x04000400, 0x00000000, 0x00000000, 0x40000000, 0x40000000, 0x00000000) { pre_idx = 1; } /* Set pre-index flag, for indexed indirect. */ \
 	t(0, 0x07101210, 0x17101410, 0x14001400, 0x10001000, 0x10000000, 0x40000000, 0x40000000, 0x00000000) { addr = ind_idx_addr(cpu, prefix, inc_clk, ZM, inc_pc, idx, pre_idx); } /* Indirect addressing, with indexing. */ \
-	t(7, 0x07561370, 0x17561570, 0x14161560, 0x10161160, 0x11161360, 0x51165161, 0x51175161, 0x01171160) { idx = 0; } /* Reset index. */ \
+	t(0, 0x07561370, 0x17561570, 0x14161560, 0x10161160, 0x11161160, 0x51165161, 0x51175161, 0x01171160) { idx = 0; } /* Reset index. */ \
 	t(0, 0x00010001, 0x00010001, 0x00010001, 0x00010001, 0x00010000, 0x00000000, 0x00000000, 0x00000000) { addr = rel_addr(cpu, prefix, inc_clk, inc_pc); } /* Relative addressing (used by conditonal branches). */ \
 	/* Load Source. */ \
 	t(0, 0x02220022, 0x03760576, 0x00220432, 0x40665076, 0x00660066, 0x04660066, 0x55665066, 0x04660066) { reg = &cpu->a; } /* Most operations use the accumulator as an operand */ \
@@ -1833,9 +1833,10 @@ static /*inline*/ void inst_##op(struct sux *cpu, uint8_t prefix, uint8_t size,
 	t(0, 0x40004000, 0x00001200, 0x12000000, 0x00001400, 0x01101510, 0x00000400, 0x00100110, 0x00000000) { reg = &cpu->x; } /* ldx, stx, cpx, inx, dex, tax, tyx, tsx */ \
 	t(0, 0x00000000, 0x40004000, 0x00041044, 0x10001200, 0x06000000, 0x00100110, 0x00000400, 0x01001000) { reg = &cpu->y; } /* ldy, sty, cpy, iny, dey, tay, txy */ \
 	t(0, 0x00000000, 0x00000000, 0x00000000, 0x04000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000) { reg = &cpu->sp; } /* txs */ \
-	t(7, 0x00010001, 0x00010001, 0x00010001, 0x00010001, 0x40014200, 0x00000200, 0x02000200, 0x02000201) { reg = (uint64_t *)&cpu->ps.u8[thread]; } /* php, test/set/clear flags, and interrupts. */ \
-	t(0, 0x07470371, 0x03470171, 0x14171561, 0x00171161, 0x10170160, 0x00160160, 0x00160160, 0x00160160) { tmp = read_value(cpu, 0, addr, rs, inc_clk, 1); } /* Read data from memory. */ \
+	t(5, 0x00010001, 0x00010001, 0x00010001, 0x00010001, 0x40014200, 0x00000200, 0x02000200, 0x02000201) { reg = (uint64_t *)&cpu->ps.u8[thread]; } /* php, test/set/clear flags, and interrupts. */ \
+	t(7, 0x07470371, 0x03470171, 0x14171561, 0x00171161, 0x10170360, 0x00160160, 0x00160160, 0x00160160) { tmp = read_value(cpu, 0, addr, rs, inc_clk, 1); } /* Read data from memory. */ \
 	t(0, 0x00000006, 0x00000006, 0x00000006, 0x00000006, 0x00000016, 0x00000016, 0x00000016, 0x00000016) { tmp = read_value(cpu, 0, cpu->pc, rs, inc_clk, 0); cpu->pc += rs+1; } /* Immediate data. */ \
+	t(7, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000200, 0x00000000, 0x00000000, 0x00000000) { addr = tmp; } /* Interrupts. */ \
 	/* Setup register transfers. */ \
 	t(0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000400, 0x00000400, 0x00000400) { reg2 = &cpu->a; } /* tab, tax, tay. */ \
 	t(0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040044, 0x00000000, 0x04000000) { reg2 = &cpu->b; } /* tba, div. */ \
@@ -1849,18 +1850,18 @@ static /*inline*/ void inst_##op(struct sux *cpu, uint8_t prefix, uint8_t size,
 	/* Store modified value into memory. */ \
 	t(0, 0x00100000, 0x04101400, 0x00100100, 0x10100100, 0x01001000, 0x51005000, 0x51005000, 0x01001000) { write_value(cpu, tmp, addr, rs, inc_clk, 1); } \
 	/* Stack related operations. */ \
-	t(7, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40004200, 0x00000000, 0x00000000, 0x00000000) { rs = 0; } /* php, plp, and interrupts. */ \
+	t(5, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40004200, 0x00000000, 0x00000000, 0x00000000) { rs = 0; } /* php, plp, and interrupts. */ \
 	t(0, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000001, 0x00000000, 0x00000000, 0x00000000) { *reg = pull(cpu, rs, thread); } /* Pull value off the stack. */ \
 	t(0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00010000, 0x00000000, 0x00000000) { cpu->pc = pull(cpu, (rs) ? rs : 7, thread); } /* Pull return address off the stack. */ \
-	t(7, 0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000200, 0x00000001, 0x00010000, 0x00000000) { push(cpu, cpu->pc, (rs) ? rs : 7, thread); } /* Push return address onto the stack. */ \
-	t(7, 0x00004000, 0x00004000, 0x00004000, 0x00004000, 0x00004200, 0x00000000, 0x00000000, 0x00000000) { push(cpu, *reg, rs, thread); } /* Push value onto the stack. */ \
+	t(5, 0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000200, 0x00000001, 0x00010000, 0x00000000) { push(cpu, cpu->pc, (rs) ? rs : 7, thread); } /* Push return address onto the stack. */ \
+	t(5, 0x00004000, 0x00004000, 0x00004000, 0x00004000, 0x00004200, 0x00000000, 0x00000000, 0x00000000) { push(cpu, *reg, rs, thread); } /* Push value onto the stack. */ \
 	/* Setting/Testing/Clearing flags, and bitwise operations. */ \
 	t(7, 0x00011001, 0x10010001, 0x00010001, 0x00010001, 0x00010200, 0x00000201, 0x02010201, 0x02010200) { tmp = 1; } \
 	t(0, 0x00000000, 0x00000001, 0x00010000, 0x00000001, 0x00010000, 0x00000000, 0x00000000, 0x00000000) { tmp <<= 1; } \
-	t(7, 0x00000001, 0x00010000, 0x00000000, 0x00000001, 0x00010200, 0x00000200, 0x02000200, 0x00000000) { tmp <<= 2; } \
+	t(5, 0x00000001, 0x00010000, 0x00000000, 0x00000001, 0x00010200, 0x00000200, 0x02000200, 0x00000000) { tmp <<= 2; } \
 	t(0, 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00010000, 0x00000000, 0x00000000, 0x00000000) { tmp <<= 4; } \
 	t(0, 0x06000000, 0x00000000, 0x04000400, 0x00441044, 0x10000000, 0x00100310, 0x00320332, 0x00100310) { tmp = ~tmp; } /* sbc, cmp, and clear flag. */ \
-	t(7, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00220222, 0x00000000, 0x02000000, 0x02000000) { tmp |= *reg; } /* ora, and set flag. */ \
+	t(5, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00220222, 0x00000000, 0x02000000, 0x02000000) { tmp |= *reg; } /* ora, and set flag. */ \
 	t(0, 0x00000001, 0x00010001, 0x00010001, 0x00010001, 0x00010000, 0x00220222, 0x00000200, 0x00000200) { tmp &= *reg; } /* AND, and clear/test flag. */ \
 	t(0, 0x00000000, 0x00000000, 0x00000000, 0x00220022, 0x00000000, 0x00000000, 0x00000000, 0x00000000) { tmp ^= *reg; } /* xor. */ \
 	/* Conditional branches. */ \
@@ -1882,7 +1883,7 @@ static /*inline*/ void inst_##op(struct sux *cpu, uint8_t prefix, uint8_t size,
 	t(0, 0x00220022, 0x00000000, 0x00220022, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000) { carry = (*reg >> (msb-(tmp2+!tmp2))) & 1; } /* rol, lsl. */ \
 	t(0, 0x00000000, 0x00220022, 0x00000000, 0x00000000, 0x00440044, 0x00000000, 0x00000000, 0x00440044) { carry = (*reg >> tmp2-(tmp2 != 0)) & 1; } /* ror, lsr, asr. */ \
 	/* Store modified value into register. */ \
-	t(7, 0x01660376, 0x03660376, 0x12261276, 0x02220232, 0x02760376, 0x00660266, 0x02660266, 0x02660267) { *reg = tmp; } \
+	t(5, 0x01660376, 0x03660376, 0x12261276, 0x02220232, 0x02760376, 0x00660266, 0x02660266, 0x02660267) { *reg = tmp; } \
 	t(0, 0x00000000, 0x00000000, 0x00000000, 0x04000400, 0x04000400, 0x04000400, 0x04000400, 0x04000400) { *reg = *reg2; } /* Register transfers. */ \
 	/* Update status flags. */ \
 	t(0, 0x00000000, 0x00000000, 0x00100100, 0x00100100, 0x00000000, 0x00000000, 0x00000000, 0x00000000) { msb = rs*8; } /* inc, dec memory. */ \