summaryrefslogtreecommitdiff
path: root/sux.c
diff options
context:
space:
mode:
Diffstat (limited to 'sux.c')
-rw-r--r--sux.c780
1 files changed, 451 insertions, 329 deletions
diff --git a/sux.c b/sux.c
index 5764807..a59e4cb 100644
--- a/sux.c
+++ b/sux.c
@@ -77,6 +77,7 @@ void *run(void *args) {
uint8_t rs;
uint8_t regsize;
uint8_t tmp;
+ uint8_t tmp2;
char *s = malloc(2048);
#if !bench
uint8_t lines = (6*thread)+2;
@@ -89,6 +90,15 @@ void *run(void *args) {
#if bench
gettimeofday(&str[thread], 0);
#endif
+#if debug && !bench
+ #if keypoll
+ pthread_mutex_lock(&mutex);
+ #endif
+ werase(scr);
+ #if keypoll
+ pthread_mutex_unlock(&mutex);
+ #endif
+#endif
while (!end) {
address = 0;
if (wai) {
@@ -115,7 +125,7 @@ void *run(void *args) {
kbd_rdy &= (uint8_t)~(1 << thread);
}
prefix = addr[cpu->pc[thread]];
- if ((prefix & 0x07) == 0x07)
+ if ((prefix & 0x03) == 0x03)
cpu->pc[thread]++;
else
prefix = 0;
@@ -142,9 +152,12 @@ void *run(void *args) {
#endif
#endif
- addrsize = (prefix & 8) == 8;
+ addrsize = (prefix & 0x0C) >> 2;
rs = (prefix & 0x30) >> 4;
- regsize = (1 << rs);
+ if (rs)
+ regsize = (1 << rs);
+ else
+ regsize = 1;
address = cpu->pc[thread];
cpu->pc[thread]++;
iclk++;
@@ -186,13 +199,29 @@ void *run(void *args) {
case ZMX:
case ZMY:
address = addr[cpu->pc[thread]];
- if (addrsize) {
- address |= addr[cpu->pc[thread]+1] << 8;
- address |= addr[cpu->pc[thread]+2] << 16;
- address |= addr[cpu->pc[thread]+3] << 24;
- cpu->pc[thread]+=4;
- } else {
- cpu->pc[thread]+=1;
+ switch (addrsize) {
+ case 3:
+ address |= addr[cpu->pc[thread]+1] << 8;
+ address |= addr[cpu->pc[thread]+2] << 16;
+ address |= addr[cpu->pc[thread]+3] << 24;
+ cpu->pc[thread]+=4;
+ break;
+ case 2:
+ address |= addr[cpu->pc[thread]+1] << 8;
+ address |= addr[cpu->pc[thread]+2] << 16;
+ address |= addr[cpu->pc[thread]+3] << 24;
+ address |= (uint64_t)addr[cpu->pc[thread]+4] << 32;
+ address |= (uint64_t)addr[cpu->pc[thread]+5] << 40;
+ cpu->pc[thread]+=6;
+ break;
+ case 1:
+ address |= addr[cpu->pc[thread]+1] << 8;
+ address |= addr[cpu->pc[thread]+2] << 16;
+ cpu->pc[thread]+=3;
+ break;
+ case 0:
+ cpu->pc[thread]+=1;
+ break;
}
tmpaddr = address;
switch (optype[opcode]) {
@@ -211,13 +240,29 @@ void *run(void *args) {
case INDX:
case INDY:
address = addr[cpu->pc[thread]];
- if (addrsize) {
- address |= addr[cpu->pc[thread]+1] << 8;
- address |= addr[cpu->pc[thread]+2] << 16;
- address |= addr[cpu->pc[thread]+3] << 24;
- cpu->pc[thread]+=4;
- } else {
- cpu->pc[thread]+=1;
+ switch (addrsize) {
+ case 3:
+ address |= addr[cpu->pc[thread]+1] << 8;
+ address |= addr[cpu->pc[thread]+2] << 16;
+ address |= addr[cpu->pc[thread]+3] << 24;
+ cpu->pc[thread]+=4;
+ break;
+ case 2:
+ address |= addr[cpu->pc[thread]+1] << 8;
+ address |= addr[cpu->pc[thread]+2] << 16;
+ address |= addr[cpu->pc[thread]+3] << 24;
+ address |= (uint64_t)addr[cpu->pc[thread]+4] << 32;
+ address |= (uint64_t)addr[cpu->pc[thread]+5] << 40;
+ cpu->pc[thread]+=6;
+ break;
+ case 1:
+ address |= addr[cpu->pc[thread]+1] << 8;
+ address |= addr[cpu->pc[thread]+2] << 16;
+ cpu->pc[thread]+=3;
+ break;
+ case 0:
+ cpu->pc[thread]+=1;
+ break;
}
iclk++;
tmpaddr = address;
@@ -245,36 +290,51 @@ void *run(void *args) {
case ABS:
address = addr[cpu->pc[thread]];
address |= addr[cpu->pc[thread]+1] << 8;
- if (addrsize) {
- address |= addr[cpu->pc[thread]+2] << 16;
- address |= addr[cpu->pc[thread]+3] << 24;
- address |= (uint64_t)addr[cpu->pc[thread]+4] << 32;
- address |= (uint64_t)addr[cpu->pc[thread]+5] << 40;
- address |= (uint64_t)addr[cpu->pc[thread]+6] << 48;
- address |= (uint64_t)addr[cpu->pc[thread]+7] << 56;
- cpu->pc[thread]+=8;
- iclk++;
- } else {
- cpu->pc[thread]+=2;
+ switch (addrsize) {
+ case 3:
+ address |= addr[cpu->pc[thread]+2] << 16;
+ address |= addr[cpu->pc[thread]+3] << 24;
+ address |= (uint64_t)addr[cpu->pc[thread]+4] << 32;
+ address |= (uint64_t)addr[cpu->pc[thread]+5] << 40;
+ address |= (uint64_t)addr[cpu->pc[thread]+6] << 48;
+ address |= (uint64_t)addr[cpu->pc[thread]+7] << 56;
+ cpu->pc[thread]+=8;
+ iclk++;
+ break;
+ case 2:
+ address |= addr[cpu->pc[thread]+2] << 16;
+ address |= addr[cpu->pc[thread]+3] << 24;
+ address |= (uint64_t)addr[cpu->pc[thread]+4] << 32;
+ address |= (uint64_t)addr[cpu->pc[thread]+5] << 40;
+ address |= (uint64_t)addr[cpu->pc[thread]+6] << 48;
+ cpu->pc[thread]+=7;
+ iclk++;
+ break;
+ case 1:
+ address |= addr[cpu->pc[thread]+2] << 16;
+ address |= addr[cpu->pc[thread]+3] << 24;
+ address |= (uint64_t)addr[cpu->pc[thread]+4] << 32;
+ cpu->pc[thread]+=5;
+ break;
+ case 0:
+ cpu->pc[thread]+=2;
+ break;
}
- iclk++;
break;
}
value = addr[address];
- if (regsize >= 2) {
- value |= addr[address+1] << 8;
- if (regsize >= 4) {
- value |= addr[address+2] << 16;
+ switch (regsize) {
+ case 8:
+ value |= (uint64_t)addr[address+7] << 56;
+ value |= (uint64_t)addr[address+6] << 48;
+ value |= (uint64_t)addr[address+5] << 40;
+ value |= (uint64_t)addr[address+4] << 32;
+ case 4:
value |= addr[address+3] << 24;
-
- if (regsize >= 8) {
- value |= (uint64_t)addr[address+4] << 32;
- value |= (uint64_t)addr[address+5] << 40;
- value |= (uint64_t)addr[address+6] << 48;
- value |= (uint64_t)addr[address+7] << 56;
- }
- }
+ value |= addr[address+2] << 16;
+ case 2:
+ value |= addr[address+1] << 8;
}
#if debug && !bench
int row, col;
@@ -324,21 +384,56 @@ void *run(void *args) {
tmpaddr = address - cpu->x[thread];
else if (optype[opcode] == ZMY)
tmpaddr = address - cpu->y[thread];
- if (addrsize)
- mvwprintw(scr, lines, col, "%s%s $%08x%s \r" , op, postfix, tmpaddr, (optype[opcode] == ZM) ? "" : ((optype[opcode] == ZMX) ? ", x" : ", y"));
- else
- mvwprintw(scr, lines, col, "%s%s $%02x%s \r" , op, postfix, tmpaddr, (optype[opcode] == ZM) ? "" : ((optype[opcode] == ZMX) ? ", x" : ", y"));
+ switch (addrsize) {
+ case 3:
+ mvwprintw(scr, lines, col, "%s%s $%08x%s \r" , op, postfix, tmpaddr, (optype[opcode] == ZM) ? "" : ((optype[opcode] == ZMX) ? ", x" : ", y"));
+ break;
+ case 2:
+ mvwprintw(scr, lines, col, "%s%s $%014llx%s \r" , op, postfix, tmpaddr, (optype[opcode] == ZM) ? "" : ((optype[opcode] == ZMX) ? ", x" : ", y"));
+ break;
+ case 1:
+ mvwprintw(scr, lines, col, "%s%s $%06x%s \r" , op, postfix, tmpaddr, (optype[opcode] == ZM) ? "" : ((optype[opcode] == ZMX) ? ", x" : ", y"));
+ break;
+ case 0:
+ mvwprintw(scr, lines, col, "%s%s $%02x%s \r" , op, postfix, tmpaddr, (optype[opcode] == ZM) ? "" : ((optype[opcode] == ZMX) ? ", x" : ", y"));
+ break;
+ }
break;
case IND:
case INDX:
case INDY:
- if (addrsize)
- mvwprintw(scr, lines, col, "%s%s ($%08x%s \r" , op, postfix, tmpaddr, (optype[opcode] == IND) ? ")" : ((optype[opcode] == INDX) ? ", x)" : "), y"));
- else
- mvwprintw(scr, lines, col, "%s%s ($%02x%s \r" , op, postfix, tmpaddr, (optype[opcode] == IND) ? ")" : ((optype[opcode] == INDX) ? ", x)" : "), y"));
+ switch (addrsize) {
+ case 3:
+ mvwprintw(scr, lines, col, "%s%s ($%08x%s \r" , op, postfix, tmpaddr, (optype[opcode] == IND) ? "" : ((optype[opcode] == INDX) ? ", x" : ", y"));
+ break;
+ case 2:
+ mvwprintw(scr, lines, col, "%s%s ($%012llx%s \r" , op, postfix, tmpaddr, (optype[opcode] == IND) ? "" : ((optype[opcode] == INDX) ? ", x" : ", y"));
+ break;
+ case 1:
+ mvwprintw(scr, lines, col, "%s%s ($%06x%s \r" , op, postfix, tmpaddr, (optype[opcode] == IND) ? "" : ((optype[opcode] == INDX) ? ", x" : ", y"));
+ break;
+ case 0:
+ mvwprintw(scr, lines, col, "%s%s ($%02x%s \r" , op, postfix, tmpaddr, (optype[opcode] == IND) ? "" : ((optype[opcode] == INDX) ? ", x" : ", y"));
+ break;
+ }
break;
case ABS:
tmpaddr = address;
+ switch (addrsize) {
+ case 3:
+ mvwprintw(scr, lines, col, "%s%s $%016x\r" , op, postfix, tmpaddr);
+ break;
+ case 2:
+ mvwprintw(scr, lines, col, "%s%s $%014llx \r" , op, postfix, tmpaddr);
+ break;
+ case 1:
+ mvwprintw(scr, lines, col, "%s%s $%010llx \r" , op, postfix, tmpaddr);
+ break;
+ case 0:
+ mvwprintw(scr, lines, col, "%s%s $%04x \r" , op, postfix, tmpaddr);
+ break;
+ }
+ break;
if (addrsize)
mvwprintw(scr, lines, col, "%s%s $%016llx\r" , op, postfix, value);
else
@@ -349,8 +444,8 @@ void *run(void *args) {
mvwprintw(scr, 29, 0, "address: $%016llx, scr_row: %02u, scr_col: %02u, scr_str: %02u, scr_end: %02u\r", address, addr[0], addr[1], addr[0x4B], addr[0x4C]);
mvwprintw(scr, 32, 0, "bitabl: %02x %02x %02x %02x %02x %02x %02x %02x "
"%02x %02x %02x %02x %02x %02x %02x %02x\r"
- , addr[0x3B], addr[0x3C], addr[0x3D], addr[0x3E], addr[0x3F], addr[0x40], addr[0x41], addr[0x42]
- , addr[0x43], addr[0x44], addr[0x45], addr[0x46], addr[0x47], addr[0x48], addr[0x49], addr[0x4A]);
+ , addr[0x16], addr[0x17], addr[0x18], addr[0x19], addr[0x1A], addr[0x1B], addr[0x1C], addr[0x1D]
+ , addr[0x1E], addr[0x1F], addr[0x20], addr[0x21], addr[0x22], addr[0x23], addr[0x24], addr[0x25]);
mvwprintw(scr, 33, 0, "buffer:\r");
uint8_t ln = 34;
uint16_t tmpad = 0x2000;
@@ -368,22 +463,34 @@ void *run(void *args) {
, i);
}
- /*tmpad = 0x4000;
+ tmpad = 0x4000;
mvwprintw(scr, ln++, 0, "cmd_buf:\r");
for (uint16_t i = 0; i < 20; i+=2) {
mvwprintw(scr, ln++, 0, "%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x "
"%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x, i: %02x\r"
- , addr[tmpad+(0x00)+(i*0x10)], addr[tmpad+(0x01)+(i*0x10)], addr[tmpad+(0x02)+(i*0x10)], addr[tmpad+(0x03)+(i*0x10)]
- , addr[tmpad+(0x04)+(i*0x10)], addr[tmpad+(0x05)+(i*0x10)], addr[tmpad+(0x06)+(i*0x10)], addr[tmpad+(0x07)+(i*0x10)]
- , addr[tmpad+(0x08)+(i*0x10)], addr[tmpad+(0x09)+(i*0x10)], addr[tmpad+(0x0A)+(i*0x10)], addr[tmpad+(0x0B)+(i*0x10)]
- , addr[tmpad+(0x0C)+(i*0x10)], addr[tmpad+(0x0D)+(i*0x10)], addr[tmpad+(0x0E)+(i*0x10)], addr[tmpad+(0x0F)+(i*0x10)]
- , addr[tmpad+(0x10)+(i*0x10)], addr[tmpad+(0x11)+(i*0x10)], addr[tmpad+(0x12)+(i*0x10)], addr[tmpad+(0x13)+(i*0x10)]
- , addr[tmpad+(0x14)+(i*0x10)], addr[tmpad+(0x15)+(i*0x10)], addr[tmpad+(0x16)+(i*0x10)], addr[tmpad+(0x17)+(i*0x10)]
- , addr[tmpad+(0x18)+(i*0x10)], addr[tmpad+(0x19)+(i*0x10)], addr[tmpad+(0x1A)+(i*0x10)], addr[tmpad+(0x1B)+(i*0x10)]
- , addr[tmpad+(0x1C)+(i*0x10)], addr[tmpad+(0x1D)+(i*0x10)], addr[tmpad+(0x1E)+(i*0x10)], addr[tmpad+(0x1F)+(i*0x10)]
+ , addr[0x4000+(0x00)+(i*0x10)], addr[0x4000+(0x01)+(i*0x10)], addr[0x4000+(0x02)+(i*0x10)], addr[0x4000+(0x03)+(i*0x10)]
+ , addr[0x4000+(0x04)+(i*0x10)], addr[0x4000+(0x05)+(i*0x10)], addr[0x4000+(0x06)+(i*0x10)], addr[0x4000+(0x07)+(i*0x10)]
+ , addr[0x4000+(0x08)+(i*0x10)], addr[0x4000+(0x09)+(i*0x10)], addr[0x4000+(0x0A)+(i*0x10)], addr[0x4000+(0x0B)+(i*0x10)]
+ , addr[0x4000+(0x0C)+(i*0x10)], addr[0x4000+(0x0D)+(i*0x10)], addr[0x4000+(0x0E)+(i*0x10)], addr[0x4000+(0x0F)+(i*0x10)]
+ , addr[0x4000+(0x10)+(i*0x10)], addr[0x4000+(0x11)+(i*0x10)], addr[0x4000+(0x12)+(i*0x10)], addr[0x4000+(0x13)+(i*0x10)]
+ , addr[0x4000+(0x14)+(i*0x10)], addr[0x4000+(0x15)+(i*0x10)], addr[0x4000+(0x16)+(i*0x10)], addr[0x4000+(0x17)+(i*0x10)]
+ , addr[0x4000+(0x18)+(i*0x10)], addr[0x4000+(0x19)+(i*0x10)], addr[0x4000+(0x1A)+(i*0x10)], addr[0x4000+(0x1B)+(i*0x10)]
+ , addr[0x4000+(0x1C)+(i*0x10)], addr[0x4000+(0x1D)+(i*0x10)], addr[0x4000+(0x1E)+(i*0x10)], addr[0x4000+(0x1F)+(i*0x10)]
, i);
- }*/
+ }
+ mvwprintw(scr, ln++, 0, "ptr: $%02x%02x%02x%02x%02x%02x%02x%02x\r"
+ , addr[0x30], addr[0x2F], addr[0x2E], addr[0x2D], addr[0x2C], addr[0x2B], addr[0x2A], addr[0x29]);
+ mvwprintw(scr, ln++, 0, "ptr2: $%02x%02x%02x%02x%02x%02x%02x%02x\r"
+ , addr[0x38], addr[0x37], addr[0x36], addr[0x35], addr[0x34], addr[0x33], addr[0x32], addr[0x31]);
+ mvwprintw(scr, ln++, 0, "ptr3: $%02x%02x%02x%02x%02x%02x%02x%02x\r"
+ , addr[0x40], addr[0x3F], addr[0x3E], addr[0x3D], addr[0x3C], addr[0x3B], addr[0x3A], addr[0x39]);
+ mvwprintw(scr, ln++, 0, "ptr4: $%02x%02x%02x%02x%02x%02x%02x%02x\r"
+ , addr[0x48], addr[0x47], addr[0x46], addr[0x45], addr[0x44], addr[0x43], addr[0x42], addr[0x41]);
+ mvwprintw(scr, ln++, 0, "ptr5: $%02x%02x%02x%02x%02x%02x%02x%02x\r"
+ , addr[0x50], addr[0x4F], addr[0x4E], addr[0x4D], addr[0x4C], addr[0x4B], addr[0x4A], addr[0x49]);
+ mvwprintw(scr, ln++, 0, "ptr6: $%02x%02x%02x%02x%02x%02x%02x%02x\r"
+ , addr[0x58], addr[0x57], addr[0x56], addr[0x55], addr[0x54], addr[0x53], addr[0x52], addr[0x51]);
wrefresh(scr);
#if keypoll
pthread_mutex_unlock(&mutex);
@@ -404,8 +511,8 @@ void *run(void *args) {
break;
case ADC: /* ADC Immediate. */
case AAB: /* Add Accumulator with carry by B register. */
- case 0x03: /* ADC Absolute. */
- case 0x05: /* ADC Zero Matrix. */
+ case ADC_AB: /* ADC Absolute. */
+ case ADC_Z: /* ADC Zero Matrix. */
if (opcode == AAB)
value = cpu->b[thread];
sum = cpu->a[thread]+value+cpu->c[thread];
@@ -440,12 +547,15 @@ void *run(void *args) {
if (tmp > 7)
tmp = 7;
- for (int8_t i = tmp<<3; i >= 0; i-=8) {
- if (i)
- addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] = reg >> i;
- else
- addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] = reg & 0xFF;
- cpu->sp[thread]--;
+ switch (tmp) {
+ case 7: addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]--] = reg >> (tmp--<<3);
+ case 6: addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]--] = reg >> (tmp--<<3);
+ case 5: addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]--] = reg >> (tmp--<<3);
+ case 4: addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]--] = reg >> (tmp--<<3);
+ case 3: addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]--] = reg >> (tmp--<<3);
+ case 2: addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]--] = reg >> (tmp--<<3);
+ case 1: addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]--] = reg >> (tmp--<<3);
+ case 0: addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]--] = reg & 0xFF;
}
break;
case TAY: /* Transfer Accumulator to Y. */
@@ -491,7 +601,7 @@ void *run(void *args) {
break;
case TXS:
cpu->sp[thread] = cpu->x[thread];
- if (prefix == 0x17 && (value == thread+1 || value > 8)) {
+ if (prefix == 0x13 && (value == thread+1 || value > 8)) {
cpu->stk_st[thread] = value & 0xFF;
cpu->stk_st[thread] += value << 16;
cpu->pc[thread]+=2;
@@ -520,12 +630,14 @@ void *run(void *args) {
setflag(cpu->n[thread], N);
break;
case JMP: /* JMP Absolute. */
+ case JMP_Z: /* JMP Zero Matrix. */
+ case JMP_IN: /* JMP Indirect. */
cpu->pc[thread] = address;
break;
case SBC: /* SBC Immediate. */
case SAB: /* Subtract Accumulator with carry by B register. */
- case 0x13: /* SBC Absolute. */
- case 0x15: /* SBC Zero Matrix. */
+ case SBC_AB: /* SBC Absolute. */
+ case SBC_Z: /* SBC Zero Matrix. */
if (opcode == SAB) {
value = cpu->b[thread];
}
@@ -559,12 +671,16 @@ void *run(void *args) {
if (tmp > 7)
tmp = 7;
- for (uint8_t i = 0; i < (tmp+1)<<3; i+=8) {
- cpu->sp[thread]++;
- if (i)
- reg += addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] << i;
- else
- reg = addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] & 0xFF;
+ tmp2 = 0;
+ cpu->sp[thread]++;reg = addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] & 0xFF;tmp2+=8;tmp--;
+ switch (tmp) {
+ case 6: cpu->sp[thread]++;reg += addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] << tmp2;tmp2+=8;
+ case 5: cpu->sp[thread]++;reg += addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] << tmp2;tmp2+=8;
+ case 4: cpu->sp[thread]++;reg += addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] << tmp2;tmp2+=8;
+ case 3: cpu->sp[thread]++;reg += addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] << tmp2;tmp2+=8;
+ case 2: cpu->sp[thread]++;reg += addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] << tmp2;tmp2+=8;
+ case 1: cpu->sp[thread]++;reg += addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] << tmp2;tmp2+=8;
+ case 0: cpu->sp[thread]++;reg += addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] << tmp2;tmp2+=8;
}
if (opcode == PLB) {
cpu->b[thread] = reg;
@@ -578,27 +694,37 @@ void *run(void *args) {
cpu->x[thread] = reg;
}
break;
- case 0x34: /* JSR Indirect. */
- case 0x44: /* JSR Indexed Indirect. */
- case 0x54: /* JSR Indirect Indexed. */
+ case JSR_IN: /* JSR Indirect. */
case JSR: /* Jump to SubRoutine. */
- if (addrsize)
+ /*if (addrsize)
stksize = 24;
else
- stksize = 0;
- for (int8_t i = stksize; i >= 0; i-=8) {
+ stksize = 0;*/
+ switch (addrsize) {
+ case 2:
+ addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] = (uint64_t)cpu->pc[thread] >> 40;cpu->sp[thread]--;
+ addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] = (uint64_t)cpu->pc[thread] >> 32;cpu->sp[thread]--;
+ case 3:
+ addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] = (uint64_t)cpu->pc[thread] >> 24;cpu->sp[thread]--;
+ case 1:
+ addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] = (uint64_t)cpu->pc[thread] >> 16;cpu->sp[thread]--;
+ addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] = (uint64_t)cpu->pc[thread] >> 8;cpu->sp[thread]--;
+ case 0:
+ addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] = (uint64_t)cpu->pc[thread] & 0xFF;cpu->sp[thread]--;
+ }
+ /*for (int8_t i = stksize; i >= 0; i-=8) {
if (i)
addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] = (uint64_t)cpu->pc[thread] >> i;
else
addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] = (uint64_t)cpu->pc[thread] & 0xFF;
cpu->sp[thread]--;
- }
+ }*/
cpu->pc[thread] = address;
break;
case AND: /* AND Immediate. */
case ABA: /* bitwise And with Accumulator, and B register. */
- case 0x23: /* AND Absolute. */
- case 0x25: /* AND Zero Matrix. */
+ case AND_AB: /* AND Absolute. */
+ case AND_Z: /* AND Zero Matrix. */
if (opcode == ABA) {
value = cpu->b[thread];
}
@@ -625,14 +751,14 @@ void *run(void *args) {
}
break;
case BPO: /* BPO Absolute. */
- case 0x64: /* BPO Zero Matrix. */
+ case BPO_Z: /* BPO Zero Matrix. */
if (!cpu->n[thread])
cpu->pc[thread] = address;
break;
case ORA: /* ORA Immediate. */
case OAB: /* bitwise Or with Accumulator, and B register. */
- case 0x33: /* ORA Absolute. */
- case 0x35: /* ORA Zero Matrix. */
+ case ORA_AB: /* ORA Absolute. */
+ case ORA_Z: /* ORA Zero Matrix. */
if (opcode == OAB) {
value = cpu->b[thread];
}
@@ -647,14 +773,14 @@ void *run(void *args) {
setflag(cpu->i[thread], I);
break;
case BNG: /* BNG Absolute. */
- case 0x74: /* BNG Zero Matrix. */
+ case BNG_Z: /* BNG Zero Matrix. */
if (cpu->n[thread])
cpu->pc[thread] = address;
break;
case XOR: /* XOR Immediate. */
case XAB: /* bitwise Xor with Accumulator, and B register. */
- case 0x43: /* XOR Absolute. */
- case 0x45: /* XOR Zero Matrix. */
+ case XOR_AB: /* XOR Absolute. */
+ case XOR_Z: /* XOR Zero Matrix. */
if (opcode == XAB) {
value = cpu->b[thread];
}
@@ -669,14 +795,14 @@ void *run(void *args) {
setflag(cpu->i[thread], I);
break;
case BCS: /* BCS Absolute. */
- case 0x84: /* BCS Zero Matrix. */
+ case BCS_Z: /* BCS Zero Matrix. */
if (cpu->c[thread])
cpu->pc[thread] = address;
break;
case LSL: /* LSL Immediate. */
case LLB: /* Logical shift Left accumulator by B. */
- case 0x53: /* LSL Absolute. */
- case 0x55: /* LSL Zero Matrix. */
+ case LSL_AB: /* LSL Absolute. */
+ case LSL_Z: /* LSL Zero Matrix. */
if (opcode == LLB) {
value = cpu->b[thread];
}
@@ -697,58 +823,55 @@ void *run(void *args) {
case STY: /* STY Absolute. */
case STX: /* STX Absolute. */
case STB: /* STB Absolute. */
- case 0x49: /* STA Zero Matrix. */
- case 0x4A: /* STY Zero Matrix. */
- case 0x4B: /* STX Zero Matrix. */
- case 0x4E: /* STB Zero Matrix. */
- case 0x69: /* STA Zero Matrix, Indexed with X. */
- case 0x6A: /* STY Zero Matrix, Indexed with X. */
- case 0x6B: /* STX Zero Matrix, Indexed with Y. */
- case 0x6E: /* STB Zero Matrix, Indexed with X. */
- case 0x89: /* STA Zero Matrix, Indexed with Y. */
- case 0x8A: /* STY Indirect. */
- case 0x8B: /* STX Indirect. */
- case 0x8E: /* STB Zero Matrix, Indexed with Y. */
- case 0xA9: /* STA Indirect. */
- case 0xAA: /* STY Indexed Indirect. */
- case 0xAB: /* STX Indirect Indexed. */
- case 0xAE: /* STB Indirect. */
- case 0xC9: /* STA Indexed Indirect. */
- case 0xCE: /* STB Indexed Indirect. */
- case 0xE9: /* STA Indirect Indexed. */
- case 0xEE: /* STB Indirect Indexed. */
+ case STA_Z: /* STA Zero Matrix. */
+ case STY_Z: /* STY Zero Matrix. */
+ case STX_Z: /* STX Zero Matrix. */
+ case STB_Z: /* STB Zero Matrix. */
+ case STA_ZX: /* STA Zero Matrix, Indexed with X. */
+ case STY_ZX: /* STY Zero Matrix, Indexed with X. */
+ case STX_ZY: /* STX Zero Matrix, Indexed with Y. */
+ case STB_ZX: /* STB Zero Matrix, Indexed with X. */
+ case STA_ZY: /* STA Zero Matrix, Indexed with Y. */
+ case STB_ZY: /* STB Zero Matrix, Indexed with Y. */
+ case STY_IN: /* STY Indirect. */
+ case STX_IN: /* STX Indirect. */
+ case STA_IN: /* STA Indirect. */
+ case STB_IN: /* STB Indirect. */
+ case STA_IX: /* STA Indexed Indirect. */
+ case STB_IX: /* STB Indexed Indirect. */
+ case STA_IY: /* STA Indirect Indexed. */
+ case STB_IY: /* STB Indirect Indexed. */
+
switch (opcode) {
case STB:
- case 0x4E:
- case 0x6E:
- case 0x8E:
- case 0xAE:
- case 0xCE:
- case 0xEE:
+ case STB_Z:
+ case STB_ZX:
+ case STB_ZY:
+ case STB_IN:
+ case STB_IX:
+ case STB_IY:
value = cpu->b[thread];
break;
case STA:
- case 0x49:
- case 0x69:
- case 0x89:
- case 0xA9:
- case 0xC9:
- case 0xE9:
+ case STA_Z:
+ case STA_ZX:
+ case STA_ZY:
+ case STA_IN:
+ case STA_IX:
+ case STA_IY:
value = cpu->a[thread];
break;
case STY:
- case 0x4A:
- case 0x6A:
- case 0x8A:
- case 0xAA:
+ case STY_Z:
+ case STY_ZX:
+ case STY_IN:
value = cpu->y[thread];
break;
case STX:
- case 0x4B:
- case 0x6B:
- case 0x8B:
- case 0xAB:
+ case STX_Z:
+ case STX_ZY:
+ case STX_IN:
value = cpu->x[thread];
break;
}
@@ -956,14 +1079,14 @@ void *run(void *args) {
}
break;
case BCC: /* BCC Absolute. */
- case 0x94: /* BCC Zero Matrix. */
+ case BCC_Z: /* BCC Zero Matrix. */
if (!cpu->c[thread])
cpu->pc[thread] = address;
break;
case LSR: /* LSR Immediate. */
case LRB: /* Logical shift Right accumulator by B. */
- case 0x63: /* LSR Absolute. */
- case 0x65: /* LSR Zero Matrix. */
+ case LSR_AB: /* LSR Absolute. */
+ case LSR_Z: /* LSR Zero Matrix. */
if (opcode == LRB) {
value = cpu->b[thread];
}
@@ -978,8 +1101,8 @@ void *run(void *args) {
break;
case ASR: /* ASR Immediate. */
case ARB: /* Arithmetic shift Right accumulator by B. */
- case 0xE3: /* ASR Absolute. */
- case 0xE5: /* ASR Zero Matrix. */
+ case ASR_AB: /* ASR Absolute. */
+ case ASR_Z: /* ASR Zero Matrix. */
if (opcode == ARB)
value = cpu->b[thread];
sign = cpu->a[thread] & 0x8000000000000000;
@@ -1000,30 +1123,28 @@ void *run(void *args) {
case LDA: /* LDA Immediate. */
case LDY: /* LDY Immediate. */
case LDX: /* LDX Immediate. */
- case 0x1E: /* LDB Absolute. */
- case 0x19: /* LDA Absolute. */
- case 0x1A: /* LDY Absolute. */
- case 0x1B: /* LDX Absolute. */
- case 0x3E: /* LDB Zero Matrix. */
- case 0x39: /* LDA Zero Matrix. */
- case 0x3A: /* LDY Zero Matrix. */
- case 0x3B: /* LDX Zero Matrix. */
- case 0x5E: /* LDB Zero Matrix, Indexed with X. */
- case 0x59: /* LDA Zero Matrix, Indexed with X. */
- case 0x5A: /* LDY Zero Matrix, Indexed with X. */
- case 0x5B: /* LDX Zero Matrix, Indexed with Y. */
- case 0x7E: /* LDB Zero Matrix, Indexed with Y. */
- case 0x79: /* LDA Zero Matrix, Indexed with Y. */
- case 0x7A: /* LDY Indirect. */
- case 0x7B: /* LDX Indirect. */
- case 0x9E: /* LDB Indirect. */
- case 0x99: /* LDA Indirect. */
- case 0x9A: /* LDY Indexed Indirect. */
- case 0x9B: /* LDX Indirect Indexed. */
- case 0xBE: /* LDB Indexed Indirect. */
- case 0xB9: /* LDA Indexed Indirect. */
- case 0xDE: /* LDB Indirect Indexed. */
- case 0xD9: /* LDA Indirect Indexed. */
+ case LDB_AB: /* LDB Absolute. */
+ case LDA_AB: /* LDA Absolute. */
+ case LDY_AB: /* LDY Absolute. */
+ case LDX_AB: /* LDX Absolute. */
+ case LDB_Z: /* LDB Zero Matrix. */
+ case LDA_Z: /* LDA Zero Matrix. */
+ case LDY_Z: /* LDY Zero Matrix. */
+ case LDX_Z: /* LDX Zero Matrix. */
+ case LDB_ZX: /* LDB Zero Matrix, Indexed with X. */
+ case LDA_ZX: /* LDA Zero Matrix, Indexed with X. */
+ case LDY_ZX: /* LDY Zero Matrix, Indexed with X. */
+ case LDX_ZY: /* LDX Zero Matrix, Indexed with Y. */
+ case LDB_ZY: /* LDB Zero Matrix, Indexed with Y. */
+ case LDA_ZY: /* LDA Zero Matrix, Indexed with Y. */
+ case LDB_IN: /* LDY Indirect. */
+ case LDA_IN: /* LDX Indirect. */
+ case LDY_IN: /* LDB Indirect. */
+ case LDX_IN: /* LDA Indirect. */
+ case LDB_IX: /* LDB Indexed Indirect. */
+ case LDA_IX: /* LDA Indexed Indirect. */
+ case LDB_IY: /* LDB Indirect Indexed. */
+ case LDA_IY: /* LDA Indirect Indexed. */
if (address == CTRL_ADDR) {
kbd_rdy = 1;
pthread_mutex_lock(&main_mutex);
@@ -1037,55 +1158,52 @@ void *run(void *args) {
kbd_rdy = 0;
}
value = addr[address];
- if (regsize >= 2) {
- value += addr[address+1] << 8;
- if (regsize >= 4) {
- value += addr[address+2] << 16;
- value += addr[address+3] << 24;
- if (regsize >= 8) {
- value += (uint64_t)addr[address+4] << 32;
- value += (uint64_t)addr[address+5] << 40;
- value += (uint64_t)addr[address+6] << 48;
- value += (uint64_t)addr[address+7] << 56;
- }
- }
+ switch (regsize) {
+ case 8:
+ value |= (uint64_t)addr[address+7] << 56;
+ value |= (uint64_t)addr[address+6] << 48;
+ value |= (uint64_t)addr[address+5] << 40;
+ value |= (uint64_t)addr[address+4] << 32;
+ case 4:
+ value |= addr[address+3] << 24;
+ value |= addr[address+2] << 16;
+ case 2:
+ value |= addr[address+1] << 8;
}
switch (opcode) {
case LDB:
- case 0x1E:
- case 0x3E:
- case 0x5E:
- case 0x7E:
- case 0x9E:
- case 0xBE:
- case 0xDE:
+ case LDB_AB:
+ case LDB_Z:
+ case LDB_ZX:
+ case LDB_ZY:
+ case LDB_IN:
+ case LDB_IX:
+ case LDB_IY:
cpu->b[thread] = value;
break;
case LDA:
- case 0x19:
- case 0x39:
- case 0x59:
- case 0x79:
- case 0x99:
- case 0xB9:
- case 0xD9:
+ case LDA_AB:
+ case LDA_Z:
+ case LDA_ZX:
+ case LDA_ZY:
+ case LDA_IN:
+ case LDA_IX:
+ case LDA_IY:
cpu->a[thread] = value;
break;
case LDY:
- case 0x1A:
- case 0x3A:
- case 0x5A:
- case 0x7A:
- case 0x9A:
+ case LDY_AB:
+ case LDY_Z:
+ case LDY_ZX:
+ case LDY_IN:
cpu->y[thread] = value;
break;
case LDX:
- case 0x1B:
- case 0x3B:
- case 0x5B:
- case 0x7B:
- case 0x9B:
+ case LDX_AB:
+ case LDX_Z:
+ case LDX_ZY:
+ case LDX_IN:
cpu->x[thread] = value;
break;
}
@@ -1095,14 +1213,14 @@ void *run(void *args) {
setflag(cpu->n[thread], N);
break;
case BEQ: /* BEQ Absolute. */
- case 0xA4: /* BEQ Zero Matrix. */
+ case BEQ_Z: /* BEQ Zero Matrix. */
if (cpu->z[thread])
cpu->pc[thread] = address;
break;
case ROL: /* ROL Immediate. */
case RLB: /* Rotate Left accumulator by B. */
- case 0x73: /* ROL Absolute. */
- case 0x75: /* ROL Zero Matrix. */
+ case ROL_AB: /* ROL Absolute. */
+ case ROL_Z: /* ROL Zero Matrix. */
if (opcode == RLB) {
value = cpu->b[thread];
}
@@ -1116,19 +1234,15 @@ void *run(void *args) {
setflag(cpu->n[thread], N);
setflag(cpu->c[thread], C);
break;
- case SSP: /* Set Stack Protection flag. */
- cpu->s[thread] = 1;
- setflag(cpu->s[thread], S);
- break;
case BNE: /* BNE Absolute. */
- case 0xB4: /* BNE Zero Matrix. */
+ case BNE_Z: /* BNE Zero Matrix. */
if (!cpu->z[thread])
cpu->pc[thread] = address;
break;
case ROR: /* ROR Immediate. */
case RRB: /* Rotate Right accumulator by B. */
- case 0x83: /* ROR Absolute. */
- case 0x85: /* ROR Zero Matrix. */
+ case ROR_AB: /* ROR Absolute. */
+ case ROR_Z: /* ROR Zero Matrix. */
if (opcode == RRB) {
value = cpu->b[thread];
}
@@ -1142,19 +1256,15 @@ void *run(void *args) {
setflag(cpu->n[thread], N);
setflag(cpu->c[thread], C);
break;
- case CSP: /* Clear Stack Protection flag. */
- cpu->s[thread] = 0;
- setflag(cpu->s[thread], S);
- break;
case BVS: /* BVS Absolute. */
- case 0xC4: /* BVS Zero Matrix. */
+ case BVS_Z: /* BVS Zero Matrix. */
if (cpu->v[thread])
cpu->pc[thread] = address;
break;
case MUL: /* MUL Immediate. */
case MAB: /* Multiply Accumulator by B. */
- case 0x93: /* MUL Absolute. */
- case 0x95: /* MUL Zero Matrix. */
+ case MUL_AB: /* MUL Absolute. */
+ case MUL_Z: /* MUL Zero Matrix. */
if (opcode == MAB) {
value = cpu->b[thread];
}
@@ -1169,19 +1279,15 @@ void *run(void *args) {
setflag(cpu->v[thread], V);
setflag(cpu->c[thread], C);
break;
- case SEV: /* SEt oVerflow flag. */
- cpu->v[thread] = 1;
- setflag(cpu->v[thread], V);
- break;
case BVC: /* BVC Absolute. */
- case 0xD4: /* BVC Zero Matrix. */
+ case BVC_Z: /* BVC Zero Matrix. */
if (!cpu->v[thread])
cpu->pc[thread] = address;
break;
case DIV: /* DIV Immediate. */
case DAB: /* Divide Accumulator by B. */
- case 0xA3: /* DIV Absolute. */
- case 0xA5: /* DIV Zero Matrix. */
+ case DIV_AB: /* DIV Absolute. */
+ case DIV_Z: /* DIV Zero Matrix. */
if (opcode != DAB) {
cpu->b[thread] = cpu->a[thread] % value;
} else {
@@ -1200,16 +1306,20 @@ void *run(void *args) {
setflag(cpu->v[thread], V);
break;
case RTS: /* ReTurn from Subroutine. */
- if (addrsize)
+ /*if (addrsize)
stksize = 32;
else
- stksize = 8;
- for (uint8_t i = 0; i < stksize; i+=8) {
- cpu->sp[thread]++;
- if (i)
- cpu->pc[thread] += addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] << i;
- else
- cpu->pc[thread] = addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]];
+ stksize = 8;*/
+ cpu->sp[thread]++;cpu->pc[thread] = addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]];
+ switch (addrsize) {
+ case 1:
+ cpu->sp[thread]++;cpu->pc[thread] += (uint64_t)addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] << 8;
+ cpu->sp[thread]++;cpu->pc[thread] += (uint64_t)addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] << 16;
+ case 3:
+ cpu->sp[thread]++;cpu->pc[thread] += (uint64_t)addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] << 24;
+ case 2:
+ cpu->sp[thread]++;cpu->pc[thread] += (uint64_t)addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] << 32;
+ cpu->sp[thread]++;cpu->pc[thread] += (uint64_t)addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] << 40;
}
break;
case CPB: /* CPB Immediate. */
@@ -1217,58 +1327,54 @@ void *run(void *args) {
case CAB: /* Compare Accumulator, and B. */
case CPY: /* CPY Immediate. */
case CPX: /* CPX Immediate. */
- case 0xCA: /* CPY Absolute. */
- case 0xCB: /* CPX Absolute. */
- case 0xB3: /* CMP Absolute. */
- case 0x36: /* CPB Absolute. */
- case 0xDA: /* CPY Zero Matrix. */
- case 0xDB: /* CPX Zero Matrix. */
- case 0xB5: /* CMP Zero Matrix. */
- case 0x46: /* CPB Zero Matrix. */
- case 0xF1: /* CMP Indirect. */
- case 0xEA: /* CPY Indirect. */
- case 0xEB: /* CPX Indirect. */
- case 0x56: /* CPB Indirect. */
- case 0xF3: /* CMP Indexed Indirect. */
- case 0xFA: /* CPY Indexed Indirect. */
- case 0x66: /* CPB Indexed Indirect. */
- case 0xF5: /* CMP Indirect Indexed. */
- case 0xFB: /* CPX Indirect Indexed. */
- case 0x76: /* CPB Indirect Indexed. */
+ case CPY_AB: /* CPY Absolute. */
+ case CPX_AB: /* CPX Absolute. */
+ case CMP_AB: /* CMP Absolute. */
+ case CPB_AB: /* CPB Absolute. */
+ case CPY_Z: /* CPY Zero Matrix. */
+ case CPX_Z: /* CPX Zero Matrix. */
+ case CMP_Z: /* CMP Zero Matrix. */
+ case CPB_Z: /* CPB Zero Matrix. */
+ case CPY_IN: /* CMP Indirect. */
+ case CPX_IN: /* CPY Indirect. */
+ case CMP_IN: /* CPX Indirect. */
+ case CPB_IN: /* CPB Indirect. */
+ case CMP_IX: /* CMP Indexed Indirect. */
+ case CPB_IX: /* CPB Indexed Indirect. */
+ case CMP_IY: /* CMP Indirect Indexed. */
+ case CPB_IY: /* CPB Indirect Indexed. */
if (opcode == CAB) {
value = cpu->b[thread];
}
switch (opcode) {
case CPB:
- case 0x36:
- case 0x46:
- case 0x56:
- case 0x66:
- case 0x76:
+ case CPB_AB:
+ case CPB_Z:
+ case CPB_IN:
+ case CPB_IX:
+ case CPB_IY:
reg = cpu->b[thread];
break;
case CMP:
case CAB:
- case 0xB3:
- case 0xB5:
- case 0xF1:
- case 0xF3:
- case 0xF5:
+ case CMP_AB:
+ case CMP_Z:
+ case CMP_IN:
+ case CMP_IX:
+ case CMP_IY:
reg = cpu->a[thread];
break;
case CPY:
- case 0xCA:
- case 0xDA:
- case 0xEA:
- case 0xFA:
+ case CPY_AB:
+ case CPY_Z:
+ case CPY_IN:
reg = cpu->y[thread];
break;
- case LDX:
- case 0xCB:
- case 0xDB:
- case 0xEB:
- case 0xFB:
+ case CPX:
+ case CPX_AB:
+ case CPX_Z:
+ case CPX_IN:
reg = cpu->x[thread];
break;
}
@@ -1300,76 +1406,82 @@ void *run(void *args) {
}
break;
case INC: /* INC Accumulator. */
- case IAB:
+ case INB:
case INY:
case INX:
- if (opcode == INC || opcode == IAB) {
- cpu->a[thread]+=1;
- if (opcode == IAB)
+ switch (opcode) {
+ case INC:
+ cpu->a[thread]+=1;
+ cpu->z[thread] = (cpu->a[thread] == 0);
+ cpu->n[thread] = (cpu->a[thread] >> 63);
+ break;
+ case INB:
cpu->b[thread]+=1;
- cpu->z[thread] = (cpu->a[thread] == 0);
- cpu->n[thread] = (cpu->a[thread] >> 63);
- }
- else if (opcode == INY) {
- cpu->y[thread]+=1;
- cpu->z[thread] = (cpu->y[thread] == 0);
- cpu->n[thread] = (cpu->y[thread] >> 63);
- }
- else if (opcode == INX) {
- cpu->x[thread]+=1;
- cpu->z[thread] = (cpu->x[thread] == 0);
- cpu->n[thread] = (cpu->x[thread] >> 63);
+ cpu->z[thread] = (cpu->b[thread] == 0);
+ cpu->n[thread] = (cpu->b[thread] >> 63);
+ break;
+ case INY:
+ cpu->y[thread]+=1;
+ cpu->z[thread] = (cpu->y[thread] == 0);
+ cpu->n[thread] = (cpu->y[thread] >> 63);
+ break;
+ case INX:
+ cpu->x[thread]+=1;
+ cpu->z[thread] = (cpu->x[thread] == 0);
+ cpu->n[thread] = (cpu->x[thread] >> 63);
+ break;
}
setflag(cpu->z[thread], Z);
setflag(cpu->n[thread], N);
break;
- case 0x04: /* JMP Indirect. */
- case 0x14: /* JMP Indexed Indirect. */
- case 0x24: /* JMP Indirect Indexed. */
- case 0xD0: /* JMP Zero Matrix. */
- cpu->pc[thread] = address;
- break;
-
case DEC: /* DEC Accumulator. */
- case DBA:
+ case DEB:
case DEY:
case DEX:
- if (opcode == DEC || opcode == DBA) {
- cpu->a[thread]-=1;
- if (opcode == DBA)
+ switch (opcode) {
+ case DEC:
+ cpu->a[thread]-=1;
+ cpu->z[thread] = (cpu->a[thread] == 0);
+ cpu->n[thread] = (cpu->a[thread] >> 63);
+ break;
+ case DEB:
cpu->b[thread]-=1;
- cpu->z[thread] = (cpu->a[thread] == 0);
- cpu->n[thread] = (cpu->a[thread] >> 63);
- }
- else if (opcode == DEY) {
- cpu->y[thread]-=1;
- cpu->z[thread] = (cpu->y[thread] == 0);
- cpu->n[thread] = (cpu->y[thread] >> 63);
- }
- else if (opcode == DEX) {
- cpu->x[thread]-=1;
- cpu->z[thread] = (cpu->x[thread] == 0);
- cpu->n[thread] = (cpu->x[thread] >> 63);
+ cpu->z[thread] = (cpu->b[thread] == 0);
+ cpu->n[thread] = (cpu->b[thread] >> 63);
+ break;
+ case DEY:
+ cpu->y[thread]-=1;
+ cpu->z[thread] = (cpu->y[thread] == 0);
+ cpu->n[thread] = (cpu->y[thread] >> 63);
+ break;
+ case DEX:
+ cpu->x[thread]-=1;
+ cpu->z[thread] = (cpu->x[thread] == 0);
+ cpu->n[thread] = (cpu->x[thread] >> 63);
+ break;
}
setflag(cpu->z[thread], Z);
setflag(cpu->n[thread], N);
break;
case JSL: /* Jump to Subroutine Long. */
- if (addrsize)
- stksize = 56;
- else
- stksize = 8;
- for (int8_t i = stksize; i >= 0; i-=8) {
- if (i)
- addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] = (uint64_t)cpu->pc[thread] >> i;
- else
- addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] = (uint64_t)cpu->pc[thread] & 0xFF;
- cpu->sp[thread]--;
+ switch (addrsize) {
+ case 3:
+ addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] = (uint64_t)cpu->pc[thread] >> 56;cpu->sp[thread]--;
+ case 2:
+ addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] = (uint64_t)cpu->pc[thread] >> 48;cpu->sp[thread]--;
+ addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] = (uint64_t)cpu->pc[thread] >> 40;cpu->sp[thread]--;
+ case 1:
+ addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] = (uint64_t)cpu->pc[thread] >> 32;cpu->sp[thread]--;
+ addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] = (uint64_t)cpu->pc[thread] >> 24;cpu->sp[thread]--;
+ addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] = (uint64_t)cpu->pc[thread] >> 16;cpu->sp[thread]--;
+ case 0:
+ addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] = (uint64_t)cpu->pc[thread] >> 8;cpu->sp[thread]--;
+ addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] = (uint64_t)cpu->pc[thread] & 0xFF;cpu->sp[thread]--;
}
cpu->pc[thread] = address;
break;
- case 0xC3: /* INC Absolute. */
- case 0xC5: /* INC Zero Matrix. */
+ case INC_AB: /* INC Absolute. */
+ case INC_Z: /* INC Zero Matrix. */
addr[address]++;
cpu->z[thread] = (addr[address] == 0);
cpu->n[thread] = (addr[address] >> 7);
@@ -1379,20 +1491,29 @@ void *run(void *args) {
case NOP: /* No OPeration. */
break;
case RTL: /* ReTurn from subroutine Long. */
- if (addrsize)
- stksize = 64;
- else
- stksize = 16;
- for (uint8_t i = 0; i < stksize; i+=8) {
+ cpu->sp[thread]++;cpu->pc[thread] = addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]];
+ cpu->sp[thread]++;cpu->pc[thread] += addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] << 8;
+ switch (addrsize) {
+ case 1:
+ cpu->sp[thread]++;cpu->pc[thread] += (uint64_t)addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] << 16;
+ cpu->sp[thread]++;cpu->pc[thread] += (uint64_t)addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] << 24;
+ cpu->sp[thread]++;cpu->pc[thread] += (uint64_t)addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] << 32;
+ case 2:
+ cpu->sp[thread]++;cpu->pc[thread] += (uint64_t)addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] << 40;
+ cpu->sp[thread]++;cpu->pc[thread] += (uint64_t)addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] << 48;
+ case 3:
+ cpu->sp[thread]++;cpu->pc[thread] += (uint64_t)addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] << 56;
+ }
+ /*for (uint8_t i = 0; i < stksize; i+=8) {
cpu->sp[thread]++;
if (i)
cpu->pc[thread] += addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]] << i;
else
cpu->pc[thread] = addr[(cpu->stk_st[thread] << 16)+cpu->sp[thread]];
- }
+ }*/
break;
- case 0xD3: /* DEC Absolute. */
- case 0xD5: /* DEC Zero Matrix. */
+ case DEC_AB: /* DEC Absolute. */
+ case DEC_Z: /* DEC Zero Matrix. */
addr[address]--;
cpu->z[thread] = (addr[address] == 0);
cpu->n[thread] = (addr[address] >> 7);
@@ -1445,6 +1566,7 @@ void *run(void *args) {
kbd_ln = 0;
else
kbd_ln = 1;
+
/*if (kbd_ln)
usleep(16666);
usleep(500000);*/