asm/TRK_MINNOW_DOLPHIN/dolphin_trk.s


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.include "macros.inc"

.section .init, "ax"  # 0x80003100 - 0x80005540
.global __TRK_reset
__TRK_reset:
/* 800051CC 000021CC  7C 08 02 A6 */	mflr r0
/* 800051D0 000021D0  90 01 00 04 */	stw r0, 4(r1)
/* 800051D4 000021D4  94 21 FF F8 */	stwu r1, -8(r1)
/* 800051D8 000021D8  48 08 69 99 */	bl __TRK_copy_vectors
/* 800051DC 000021DC  38 21 00 08 */	addi r1, r1, 8
/* 800051E0 000021E0  80 01 00 04 */	lwz r0, 4(r1)
/* 800051E4 000021E4  7C 08 03 A6 */	mtlr r0
/* 800051E8 000021E8  4E 80 00 20 */	blr 

.section .text, "ax"  # 0x80005600 - 0x8036FBA0
.global InitMetroTRK
InitMetroTRK:
/* 8008BA14 00088954  38 21 FF FC */	addi r1, r1, -4
/* 8008BA18 00088958  90 61 00 00 */	stw r3, 0(r1)
/* 8008BA1C 0008895C  3C 60 80 3E */	lis r3, gTRKCPUState@h
/* 8008BA20 00088960  60 63 AC 30 */	ori r3, r3, gTRKCPUState@l
/* 8008BA24 00088964  BC 03 00 00 */	stmw r0, 0(r3)
/* 8008BA28 00088968  80 81 00 00 */	lwz r4, 0(r1)
/* 8008BA2C 0008896C  38 21 00 04 */	addi r1, r1, 4
/* 8008BA30 00088970  90 23 00 04 */	stw r1, 4(r3)
/* 8008BA34 00088974  90 83 00 0C */	stw r4, 0xc(r3)
/* 8008BA38 00088978  7C 88 02 A6 */	mflr r4
/* 8008BA3C 0008897C  90 83 00 84 */	stw r4, 0x84(r3)
/* 8008BA40 00088980  90 83 00 80 */	stw r4, 0x80(r3)
/* 8008BA44 00088984  7C 80 00 26 */	mfcr r4
/* 8008BA48 00088988  90 83 00 88 */	stw r4, 0x88(r3)
/* 8008BA4C 0008898C  7C 80 00 A6 */	mfmsr r4
/* 8008BA50 00088990  60 83 80 00 */	ori r3, r4, 0x8000
/* 8008BA54 00088994  68 63 80 00 */	xori r3, r3, 0x8000
/* 8008BA58 00088998  7C 60 01 24 */	mtmsr r3
/* 8008BA5C 0008899C  7C 9B 03 A6 */	mtspr 0x1b, r4
/* 8008BA60 000889A0  48 00 01 F5 */	bl TRKSaveExtended1Block
/* 8008BA64 000889A4  3C 60 80 3E */	lis r3, gTRKCPUState@h
/* 8008BA68 000889A8  60 63 AC 30 */	ori r3, r3, gTRKCPUState@l
/* 8008BA6C 000889AC  B8 03 00 00 */	.4byte 0xB8030000  /* illegal lmw r0, 0(r3) */
/* 8008BA70 000889B0  38 00 00 00 */	li r0, 0
/* 8008BA74 000889B4  7C 12 FB A6 */	mtspr 0x3f2, r0
/* 8008BA78 000889B8  7C 15 FB A6 */	mtspr 0x3f5, r0
/* 8008BA7C 000889BC  3C 20 80 42 */	lis r1, 0x80426008@h
/* 8008BA80 000889C0  60 21 60 08 */	ori r1, r1, 0x80426008@l
/* 8008BA84 000889C4  7C A3 2B 78 */	mr r3, r5
/* 8008BA88 000889C8  48 00 06 4D */	bl InitMetroTRKCommTable
/* 8008BA8C 000889CC  2C 03 00 01 */	cmpwi r3, 1
/* 8008BA90 000889D0  40 82 00 14 */	bne lbl_8008BAA4
/* 8008BA94 000889D4  80 83 00 84 */	lwz r4, 0x84(r3)
/* 8008BA98 000889D8  7C 88 03 A6 */	mtlr r4
/* 8008BA9C 000889DC  B8 03 00 00 */	.4byte 0xB8030000  /* illegal lmw r0, 0(r3) */
/* 8008BAA0 000889E0  4E 80 00 20 */	blr 
lbl_8008BAA4:
/* 8008BAA4 000889E4  48 00 05 28 */	b TRK_main

.global EnableMetroTRKInterrupts
EnableMetroTRKInterrupts:
/* 8008BAA8 000889E8  7C 08 02 A6 */	mflr r0
/* 8008BAAC 000889EC  90 01 00 04 */	stw r0, 4(r1)
/* 8008BAB0 000889F0  94 21 FF F8 */	stwu r1, -8(r1)
/* 8008BAB4 000889F4  48 00 07 4D */	bl EnableEXI2Interrupts
/* 8008BAB8 000889F8  38 21 00 08 */	addi r1, r1, 8
/* 8008BABC 000889FC  80 01 00 04 */	lwz r0, 4(r1)
/* 8008BAC0 00088A00  7C 08 03 A6 */	mtlr r0
/* 8008BAC4 00088A04  4E 80 00 20 */	blr 

.global TRKTargetTranslate
TRKTargetTranslate:
/* 8008BAC8 00088A08  3C 80 80 3F */	lis r4, lc_base@ha
/* 8008BACC 00088A0C  38 84 B0 60 */	addi r4, r4, lc_base@l
/* 8008BAD0 00088A10  80 84 00 00 */	lwz r4, 0(r4)
/* 8008BAD4 00088A14  7C 03 20 40 */	cmplw r3, r4
/* 8008BAD8 00088A18  41 80 00 2C */	blt lbl_8008BB04
/* 8008BADC 00088A1C  38 04 40 00 */	addi r0, r4, 0x4000
/* 8008BAE0 00088A20  7C 03 00 40 */	cmplw r3, r0
/* 8008BAE4 00088A24  40 80 00 20 */	bge lbl_8008BB04
/* 8008BAE8 00088A28  3C 80 80 3F */	lis r4, gTRKCPUState@ha
/* 8008BAEC 00088A2C  38 84 AC 30 */	addi r4, r4, gTRKCPUState@l
/* 8008BAF0 00088A30  80 04 02 38 */	lwz r0, 0x238(r4)
/* 8008BAF4 00088A34  54 00 07 BE */	clrlwi r0, r0, 0x1e
/* 8008BAF8 00088A38  28 00 00 00 */	cmplwi r0, 0
/* 8008BAFC 00088A3C  41 82 00 08 */	beq lbl_8008BB04
/* 8008BB00 00088A40  48 00 00 0C */	b lbl_8008BB0C
lbl_8008BB04:
/* 8008BB04 00088A44  54 60 00 BE */	clrlwi r0, r3, 2
/* 8008BB08 00088A48  64 03 80 00 */	oris r3, r0, 0x8000
lbl_8008BB0C:
/* 8008BB0C 00088A4C  4E 80 00 20 */	blr 

.global TRK_copy_vector
TRK_copy_vector:
/* 8008BB10 00088A50  7C 08 02 A6 */	mflr r0
/* 8008BB14 00088A54  90 01 00 04 */	stw r0, 4(r1)
/* 8008BB18 00088A58  94 21 FF F0 */	stwu r1, -0x10(r1)
/* 8008BB1C 00088A5C  93 E1 00 0C */	stw r31, 0xc(r1)
/* 8008BB20 00088A60  93 C1 00 08 */	stw r30, 8(r1)
/* 8008BB24 00088A64  7C 7E 1B 78 */	mr r30, r3
/* 8008BB28 00088A68  7F C3 F3 78 */	mr r3, r30
/* 8008BB2C 00088A6C  4B FF FF 9D */	bl TRKTargetTranslate
/* 8008BB30 00088A70  3C 80 80 00 */	lis r4, lbl_80003298@ha
/* 8008BB34 00088A74  38 04 32 98 */	addi r0, r4, lbl_80003298@l
/* 8008BB38 00088A78  7C 7F 1B 78 */	mr r31, r3
/* 8008BB3C 00088A7C  7C 80 F2 14 */	add r4, r0, r30
/* 8008BB40 00088A80  7F E3 FB 78 */	mr r3, r31
/* 8008BB44 00088A84  38 A0 01 00 */	li r5, 0x100
/* 8008BB48 00088A88  4B F7 76 FD */	bl TRK_memcpy
/* 8008BB4C 00088A8C  7F E3 FB 78 */	mr r3, r31
/* 8008BB50 00088A90  38 80 01 00 */	li r4, 0x100
/* 8008BB54 00088A94  4B FF E7 E9 */	bl TRK_flush_cache
/* 8008BB58 00088A98  83 E1 00 0C */	lwz r31, 0xc(r1)
/* 8008BB5C 00088A9C  83 C1 00 08 */	lwz r30, 8(r1)
/* 8008BB60 00088AA0  38 21 00 10 */	addi r1, r1, 0x10
/* 8008BB64 00088AA4  80 01 00 04 */	lwz r0, 4(r1)
/* 8008BB68 00088AA8  7C 08 03 A6 */	mtlr r0
/* 8008BB6C 00088AAC  4E 80 00 20 */	blr 

.global __TRK_copy_vectors
__TRK_copy_vectors:
/* 8008BB70 00088AB0  7C 08 02 A6 */	mflr r0
/* 8008BB74 00088AB4  90 01 00 04 */	stw r0, 4(r1)
/* 8008BB78 00088AB8  94 21 FF E8 */	stwu r1, -0x18(r1)
/* 8008BB7C 00088ABC  93 E1 00 14 */	stw r31, 0x14(r1)
/* 8008BB80 00088AC0  93 C1 00 10 */	stw r30, 0x10(r1)
/* 8008BB84 00088AC4  93 A1 00 0C */	stw r29, 0xc(r1)
/* 8008BB88 00088AC8  93 81 00 08 */	stw r28, 8(r1)
/* 8008BB8C 00088ACC  38 60 00 44 */	li r3, 0x44
/* 8008BB90 00088AD0  4B FF FF 39 */	bl TRKTargetTranslate
/* 8008BB94 00088AD4  3B A0 00 00 */	li r29, 0
/* 8008BB98 00088AD8  83 83 00 00 */	lwz r28, 0(r3)
/* 8008BB9C 00088ADC  3C 60 80 3B */	lis r3, TRK_ISR_OFFSETS@ha
/* 8008BBA0 00088AE0  57 A4 10 3A */	slwi r4, r29, 2
/* 8008BBA4 00088AE4  38 03 F0 48 */	addi r0, r3, TRK_ISR_OFFSETS@l
/* 8008BBA8 00088AE8  7F C0 22 14 */	add r30, r0, r4
/* 8008BBAC 00088AEC  48 00 00 04 */	b lbl_8008BBB0
lbl_8008BBB0:
/* 8008BBB0 00088AF0  3B E0 00 01 */	li r31, 1
/* 8008BBB4 00088AF4  48 00 00 04 */	b lbl_8008BBB8
lbl_8008BBB8:
/* 8008BBB8 00088AF8  48 00 00 04 */	b lbl_8008BBBC
lbl_8008BBBC:
/* 8008BBBC 00088AFC  7F E0 E8 30 */	slw r0, r31, r29
/* 8008BBC0 00088B00  7F 80 00 38 */	and r0, r28, r0
/* 8008BBC4 00088B04  28 00 00 00 */	cmplwi r0, 0
/* 8008BBC8 00088B08  41 82 00 0C */	beq lbl_8008BBD4
/* 8008BBCC 00088B0C  80 7E 00 00 */	lwz r3, 0(r30)
/* 8008BBD0 00088B10  4B FF FF 41 */	bl TRK_copy_vector
lbl_8008BBD4:
/* 8008BBD4 00088B14  3B DE 00 04 */	addi r30, r30, 4
/* 8008BBD8 00088B18  3B BD 00 01 */	addi r29, r29, 1
/* 8008BBDC 00088B1C  2C 1D 00 0E */	cmpwi r29, 0xe
/* 8008BBE0 00088B20  40 81 FF DC */	ble lbl_8008BBBC
/* 8008BBE4 00088B24  83 E1 00 14 */	lwz r31, 0x14(r1)
/* 8008BBE8 00088B28  83 C1 00 10 */	lwz r30, 0x10(r1)
/* 8008BBEC 00088B2C  83 A1 00 0C */	lwz r29, 0xc(r1)
/* 8008BBF0 00088B30  83 81 00 08 */	lwz r28, 8(r1)
/* 8008BBF4 00088B34  38 21 00 18 */	addi r1, r1, 0x18
/* 8008BBF8 00088B38  80 01 00 04 */	lwz r0, 4(r1)
/* 8008BBFC 00088B3C  7C 08 03 A6 */	mtlr r0
/* 8008BC00 00088B40  4E 80 00 20 */	blr 

.global TRKInitializeTarget
TRKInitializeTarget:
/* 8008BC04 00088B44  7C 08 02 A6 */	mflr r0
/* 8008BC08 00088B48  90 01 00 04 */	stw r0, 4(r1)
/* 8008BC0C 00088B4C  94 21 FF F0 */	stwu r1, -0x10(r1)
/* 8008BC10 00088B50  93 E1 00 0C */	stw r31, 0xc(r1)
/* 8008BC14 00088B54  3C 60 80 3F */	lis r3, gTRKState@ha
/* 8008BC18 00088B58  3B E3 AB 88 */	addi r31, r3, gTRKState@l
/* 8008BC1C 00088B5C  38 00 00 01 */	li r0, 1
/* 8008BC20 00088B60  90 1F 00 98 */	stw r0, 0x98(r31)
/* 8008BC24 00088B64  4B FF E8 15 */	bl __TRK_get_MSR
/* 8008BC28 00088B68  90 7F 00 8C */	stw r3, 0x8c(r31)
/* 8008BC2C 00088B6C  3C 60 80 3F */	lis r3, lc_base@ha
/* 8008BC30 00088B70  38 63 B0 60 */	addi r3, r3, lc_base@l
/* 8008BC34 00088B74  3C 00 E0 00 */	lis r0, 0xe000
/* 8008BC38 00088B78  90 03 00 00 */	stw r0, 0(r3)
/* 8008BC3C 00088B7C  38 60 00 00 */	li r3, 0
/* 8008BC40 00088B80  83 E1 00 0C */	lwz r31, 0xc(r1)
/* 8008BC44 00088B84  38 21 00 10 */	addi r1, r1, 0x10
/* 8008BC48 00088B88  80 01 00 04 */	lwz r0, 4(r1)
/* 8008BC4C 00088B8C  7C 08 03 A6 */	mtlr r0
/* 8008BC50 00088B90  4E 80 00 20 */	blr 

.section .data, "wa"  # 0x803A8380 - 0x803E6000
TRK_ISR_OFFSETS:
	.4byte 0x00000100
	.4byte 0x00000200
	.4byte 0x00000300
	.4byte 0x00000400
	.4byte 0x00000500
	.4byte 0x00000600
	.4byte 0x00000700
	.4byte 0x00000800
	.4byte 0x00000900
	.4byte 0x00000C00
	.4byte 0x00000D00
	.4byte 0x00000F00
	.4byte 0x00001300
	.4byte 0x00001400
	.4byte 0x00001700
	.4byte 0

.section .bss, "wa"  # 0x803E6000 - 0x80408AC0
lc_base:
	.skip 0x8