asm/TRK_MINNOW_DOLPHIN/mem_TRK.s


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.include "macros.inc"

.section .init, "ax"  # 0x80003100 - 0x80005540
.global TRK_memcpy
TRK_memcpy:
/* 80003244 00000244  38 84 FF FF */	addi r4, r4, -1
/* 80003248 00000248  38 C3 FF FF */	addi r6, r3, -1
/* 8000324C 0000024C  38 A5 00 01 */	addi r5, r5, 1
/* 80003250 00000250  48 00 00 0C */	b lbl_8000325C
lbl_80003254:
/* 80003254 00000254  8C 04 00 01 */	lbzu r0, 1(r4)
/* 80003258 00000258  9C 06 00 01 */	stbu r0, 1(r6)
lbl_8000325C:
/* 8000325C 0000025C  34 A5 FF FF */	addic. r5, r5, -1
/* 80003260 00000260  40 82 FF F4 */	bne lbl_80003254
/* 80003264 00000264  4E 80 00 20 */	blr 

.global TRK_memset
TRK_memset:
/* 80003268 00000268  7C 08 02 A6 */	mflr r0
/* 8000326C 0000026C  90 01 00 04 */	stw r0, 4(r1)
/* 80003270 00000270  94 21 FF F0 */	stwu r1, -0x10(r1)
/* 80003274 00000274  93 E1 00 0C */	stw r31, 0xc(r1)
/* 80003278 00000278  7C 7F 1B 78 */	mr r31, r3
/* 8000327C 0000027C  48 08 70 F9 */	bl TRK_fill_mem
/* 80003280 00000280  7F E3 FB 78 */	mr r3, r31
/* 80003284 00000284  83 E1 00 0C */	lwz r31, 0xc(r1)
/* 80003288 00000288  38 21 00 10 */	addi r1, r1, 0x10
/* 8000328C 0000028C  80 01 00 04 */	lwz r0, 4(r1)
/* 80003290 00000290  7C 08 03 A6 */	mtlr r0
/* 80003294 00000294  4E 80 00 20 */	blr 

.section .text, "ax"  # 0x80005600 - 0x8036FBA0
.global TRK_fill_mem
TRK_fill_mem:
/* 8008A374 000872B4  28 05 00 20 */	cmplwi r5, 0x20
/* 8008A378 000872B8  38 C3 FF FF */	addi r6, r3, -1
/* 8008A37C 000872BC  54 80 06 3E */	clrlwi r0, r4, 0x18
/* 8008A380 000872C0  7C 07 03 78 */	mr r7, r0
/* 8008A384 000872C4  41 80 00 98 */	blt lbl_8008A41C
/* 8008A388 000872C8  7C C0 30 F8 */	nor r0, r6, r6
/* 8008A38C 000872CC  54 00 07 BF */	clrlwi. r0, r0, 0x1e
/* 8008A390 000872D0  7C 03 03 78 */	mr r3, r0
/* 8008A394 000872D4  41 82 00 18 */	beq lbl_8008A3AC
/* 8008A398 000872D8  7C A3 28 50 */	subf r5, r3, r5
/* 8008A39C 000872DC  54 E0 06 3E */	clrlwi r0, r7, 0x18
lbl_8008A3A0:
/* 8008A3A0 000872E0  34 63 FF FF */	addic. r3, r3, -1
/* 8008A3A4 000872E4  9C 06 00 01 */	stbu r0, 1(r6)
/* 8008A3A8 000872E8  40 82 FF F8 */	bne lbl_8008A3A0
lbl_8008A3AC:
/* 8008A3AC 000872EC  28 07 00 00 */	cmplwi r7, 0
/* 8008A3B0 000872F0  41 82 00 1C */	beq lbl_8008A3CC
/* 8008A3B4 000872F4  54 E3 C0 0E */	slwi r3, r7, 0x18
/* 8008A3B8 000872F8  54 E0 80 1E */	slwi r0, r7, 0x10
/* 8008A3BC 000872FC  54 E4 40 2E */	slwi r4, r7, 8
/* 8008A3C0 00087300  7C 60 03 78 */	or r0, r3, r0
/* 8008A3C4 00087304  7C 80 03 78 */	or r0, r4, r0
/* 8008A3C8 00087308  7C E7 03 78 */	or r7, r7, r0
lbl_8008A3CC:
/* 8008A3CC 0008730C  54 A0 D9 7F */	rlwinm. r0, r5, 0x1b, 5, 0x1f
/* 8008A3D0 00087310  38 66 FF FD */	addi r3, r6, -3
/* 8008A3D4 00087314  41 82 00 2C */	beq lbl_8008A400
lbl_8008A3D8:
/* 8008A3D8 00087318  90 E3 00 04 */	stw r7, 4(r3)
/* 8008A3DC 0008731C  34 00 FF FF */	addic. r0, r0, -1
/* 8008A3E0 00087320  90 E3 00 08 */	stw r7, 8(r3)
/* 8008A3E4 00087324  90 E3 00 0C */	stw r7, 0xc(r3)
/* 8008A3E8 00087328  90 E3 00 10 */	stw r7, 0x10(r3)
/* 8008A3EC 0008732C  90 E3 00 14 */	stw r7, 0x14(r3)
/* 8008A3F0 00087330  90 E3 00 18 */	stw r7, 0x18(r3)
/* 8008A3F4 00087334  90 E3 00 1C */	stw r7, 0x1c(r3)
/* 8008A3F8 00087338  94 E3 00 20 */	stwu r7, 0x20(r3)
/* 8008A3FC 0008733C  40 82 FF DC */	bne lbl_8008A3D8
lbl_8008A400:
/* 8008A400 00087340  54 A0 F7 7F */	rlwinm. r0, r5, 0x1e, 0x1d, 0x1f
/* 8008A404 00087344  41 82 00 10 */	beq lbl_8008A414
lbl_8008A408:
/* 8008A408 00087348  34 00 FF FF */	addic. r0, r0, -1
/* 8008A40C 0008734C  94 E3 00 04 */	stwu r7, 4(r3)
/* 8008A410 00087350  40 82 FF F8 */	bne lbl_8008A408
lbl_8008A414:
/* 8008A414 00087354  38 C3 00 03 */	addi r6, r3, 3
/* 8008A418 00087358  54 A5 07 BE */	clrlwi r5, r5, 0x1e
lbl_8008A41C:
/* 8008A41C 0008735C  28 05 00 00 */	cmplwi r5, 0
/* 8008A420 00087360  4D 82 00 20 */	beqlr 
/* 8008A424 00087364  54 E0 06 3E */	clrlwi r0, r7, 0x18
lbl_8008A428:
/* 8008A428 00087368  34 A5 FF FF */	addic. r5, r5, -1
/* 8008A42C 0008736C  9C 06 00 01 */	stbu r0, 1(r6)
/* 8008A430 00087370  40 82 FF F8 */	bne lbl_8008A428
/* 8008A434 00087374  4E 80 00 20 */	blr